feature article
Subscribe Now

Blasting Billions of Bits

Xilinx Introduces Virtex-5 TXT

The other day, I was killing five minutes between briefings by watching a YouTube video on my iPhone.  Right in the middle of the video (the funniest part, in fact) my viewing was interrupted by a text message from my wife (a photographer by trade).  The message read:

“Looks like my Terabyte is full.”

As we go through our day-to-day lives, our perspective on certain things shifts gradually – sometimes too slowly for us to notice.  For most of my life, I’ve lived in a reality that includes Moore’s Law.  When constant exponential change is our status-quo baseline, it can distort our perception in a way that makes for occasional shocking surprises. 

When, exactly, did I reach the point where I was “adjusted” to the idea that a single individual, working in a non-technology job, could create over a terabyte of data in the course of a year or so of their normal work.  If I do the math, of course, it all adds up.  In a typical studio session, she captures maybe 300 images in an hour.  Each RAW image is maybe 14MB.  The images that become “selects” are also saved as Photoshop documents that can easily exceed 100MB each.  Archive all that information over the course of all the studio sessions in a year… How did the Terabyte last so long?

If she worked in video, of course, the problem would be an order of magnitude worse.  Multiply this data explosion by the millions that are creating data-laden content.  Now, push that content across the internet for consumption, connect it to a server farm for cloud storage, and stream it to millions of mobile devices that are now sucking up bandwidth at an unprecedented rate.  This is not your grandfather’s bandwidth problem.  In fact, it’s not even your father’s… or even your own two years ago. 

As we know, all this data has to be pushed through a series of tubes, and the demands on those tubes has grown enormously over the past couple of years.  The companies in charge of the construction and maintenance of those tubes have always been pushing the limits of FPGA capability.  In fact, network data communication has historically been one of the main drivers of the FPGA market.  Every time FPGA companies came up with bigger faster devices with bigger faster data pipes, these guys still wanted more for less – more data capacity, less power, less cost, less board area.

Xilinx recently made a big jump in the “more for less” department with the announcement of their new Virtex-5 TXT family. 

The short version?  

Xilinx has created a new Virtex-5 variant that basically doubles the number of transceivers available.

By the numbers, the new TXT platform has 48 GTX 6.5 Gbps transceivers providing an aggregated bandwidth of over 600Gbps.  They accomplish this at a very respectable “less than 200mW per channel at 6.5Gbps” power consumption.  This expansion allows a single FPGA to do the work of two or more in today’s predominant bandwidth-hog applications such as pushing 100G Ethernet, 120G Interlaken and the like.

Saving a whole high-end FPGA in these designs is an enormous cost, footprint, complexity, and power savings for the high-throughput applications of those guys that are expanding the tubes to meet all the data-moving requirements for people like… my wife.

Xilinx accomplished the engineering on this new platform in record time, largely owing to their so-called “ASMBL” architecture.  We first heard of ASMBL back before Virtex-4 arrived.  The idea, according to Xilinx at the time, was that FPGAs could be built from a column-based mix-and-match architecture.  A number of columns could be designed with different mixes of features – some with simple LUT fabric, some with more mulitpliers, some with more memory, and some with multi-gigabit serial transceivers.  Creating a customized FPGA then was a comparatively simple matter of stitching together columns that gave one the desired mix of features.  From the perspective of designing and verifying a new FPGA device, this reduced the complexity considerably.  Helping this idea along was the advent of flip-chip packaging for FPGAs, obviating the need for a traditional I/O ring.  Without the I/O ring constraints, the column-based building-block architecture was fully enabled.

In the past, the advantages of ASMBL were largely hidden from the public.  Sure, Xilinx rolled out Virtex-5 with a whopping array of variants, but ASMBL was hiding in the background – mostly reducing Xilinx’s headaches.  This time, however, customers came to the company and said “Hey, Help!  We need more transceivers!” and Xilinx said “OK, we’ll whip out a new FPGA with twice as many.  Need anything else?”  OK, maybe that wasn’t the exact conversation, but ASMBL came through, engineers dropped in more columns of already-proven transceivers, and now we have Virtex-5 TXT.

Xilinx doesn’t leave the benefits of TXT to our imagination – they provide a number of solid customer case studies that clearly show the absorption of many FPGAs into one – 100G Ethernet MAC-to-Interlaken Bridge, 40G Quad XAUI to Interlaken Bridge, 40G OC-768 to OTU-3 Bridge, 32-Port Digital Video Switch…  The list goes on.  Basically, any time you need to connect “Part A” in one domain to “Part B” in another via a very high-bandwidth connection, TXT provides more than half of a Tbps of capacity (sorry, we’d never used that abbreviation before — we just had to go for it) in a single device.

Xilinx says that we can start designing with Virtex-5 TXT immediately.  The documentation is available for download, key IP is available (such as pre-engineered blocks for popular protocols) and the new family is already supported by the ISE Design Suite v10.1, SP3.  Device samples will be available in December 2008, with volume production in February 2009.  The TX240T (240K logic cell equivalent with 48 transceivers, 12Kb of block RAM, and 96 DSP slices) in the FF1759 package will be the first device available, followed by the TX150T (150K LUT equivalent with 40 transceivers, 8Kb of block RAM, and 80 DSP slices).

We expect the new family to be a welcome option for developers of super-high-bandwidth applications, as the alternatives (ASSPs, more FPGAs, ASICs) are all either not available, much more expensive, and/or much higher risk.  Xilinx’s ASMBL architecture has now proven that the company can be nimble in responding to changing market demands, bringing a high-value solution to market in very short order.

Leave a Reply

featured blogs
May 7, 2021
In one of our Knowledge Booster Blogs a few months ago we introduced you to some tips and tricks for the optimal use of Virtuoso ADE Product Suite with our analog IC design videos . W e hope you... [[ Click on the title to access the full blog on the Cadence Community site. ...
May 7, 2021
Enough of the letter “P” already. Message recieved. In any case, modeling and simulating next-gen 224 Gbps signal channels poses many challenges. Design engineers must optimize the entire signal path, not just a specific component. The signal path includes transce...
May 6, 2021
Learn how correct-by-construction coding enables a more productive chip design process, as new code review tools address bugs early in the design process. The post Find Bugs Earlier Via On-the-Fly Code Checking for Productive Chip Design and Verification appeared first on Fr...
May 4, 2021
What a difference a year can make! Oh, we're not referring to that virus that… The post Realize Live + U2U: Side by Side appeared first on Design with Calibre....

featured video

The Verification World We Know is About to be Revolutionized

Sponsored by Cadence Design Systems

Designs and software are growing in complexity. With verification, you need the right tool at the right time. Cadence® Palladium® Z2 emulation and Protium™ X2 prototyping dynamic duo address challenges of advanced applications from mobile to consumer and hyperscale computing. With a seamlessly integrated flow, unified debug, common interfaces, and testbench content across the systems, the dynamic duo offers rapid design migration and testing from emulation to prototyping. See them in action.

Click here for more information

featured paper

Optimizing an OpenCL AI Kernel for the data center using Silexica’s SLX FPGA

Sponsored by Silexica

AI applications are increasingly contributing to FPGAs being used as co-processors in data centers. Silexica's newest application note shows how SLX FPGA accelerates an AI-related face detection design example, leveraging the bottom-up flow of Xilinx’s Vitis 2020.2 and Alveo U280 accelerator card.

Click to read

Featured Chalk Talk

Single Pair Ethernet

Sponsored by Mouser Electronics and HARTING

Industry 4.0 brings serious demands on communication connections. Designers need to consider interoperability, processing, analytics, EMI reduction, field rates, communication protocols and much more. In this episode of Chalk Talk, Amelia Dalton chats with Piotr Polak and McKenzie Reed of Harting about using single-pair Ethernet for Industry 4.0.

Click here for more information about HARTING T1 Industrial Single Pair Ethernet (SPE) Products