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Citius, Altius, Fortius

XAP5 Goes for Gold

Better, stronger, faster. Isn’t that what every new microprocessor is supposed to deliver? Hope springs eternal in the breast of many a processor-marketing drone. Their new chip isn’t just better than the previous one, it’s better than everyone else’s, too.

And you know, sometimes that promise actually comes true. A case in point is the XAP5 processor from Cambridge Consultants, a company of consultants located in – wait for it – Cambridge, England. Actually, they’re located in Cambridge, Massachusetts as well, a choice of venue that’s both convenient and confusing. Either way, this bicoastal team of engineers has cooked up a fifth generation of their XAP processor, a 16-bit CPU designed to minimize both power consumption and code space.

XAP5 is no mere tweak, nor is Cambridge Consultants your run-of-the-mill house for frequently unemployed geeks and frustrated processor designers. Au contraire, the firm employs more than 300 engineers from all disciplines (mechanical engineers, industrial designers, programmers, etc.), and the company has already shipped its billionth (that’s with a B) XAP processor. Most of the world’s Bluetooth headsets and Bluetooth-enabled phones have an embedded XAP processor, according to the company. That puts XAP’s all-time sales volume in the same league as the venerable 68K, x86, and 6805 processors. In other words, XAP is no mere science project. It may just be the most popular processor you’ve never heard of.

That’s swell, but what does XAP5 do for today’s struggling programmer or hardware engineer? Quite a lot, really, if said programmer/engineer is willing to design an ASIC around the XAP5 core. You see, XAP5 isn’t available as a packaged chip, only as licensed IP. That means that, unless you’re taking on the crushing cost and complexity of an ASIC-development project, XAP5 isn’t for you. That’s a shame, because it would be a great little processor for a range of low-cost but high-volume products.

Since you’ve made it this far, let’s assume that you are shopping for an ASIC-friendly processor core for your next project. There are lots of choices, starting with cross-town rival ARM and its ubiquitous line of Cortex processor cores. ARM is the hands-down (sorry) winner in terms of popularity. There are more ARM-based chips sold each month than Intel produces all year. Popularity is ARM’s middle name. So is price; ARM cores are expensive. Although Cambridge Consultants doesn’t disclose its price list, its license fees are “significantly below” ARM’s. They’d have to be.

The XAP5 also has technical merit in its favor. According to its creators, XAP5 has better code density (that is, a smaller memory footprint) than ARM’s Cortex-M3, while delivering similar performance. XAP5 also works better with flash memory, a characteristic that’s become increasingly important to embedded chip designers. As flash gets cheaper and faster, it’s becoming the primary memory type in some systems. XAP5 is designed specifically to execute code directly from flash memory, avoiding the cost and complication of copying everything to RAM. To a great extent, flash could be your only memory in the system.

The programming model for XAP5 is pretty straightforward. It’s basically a 16-bit processor with eight 16-bit registers and a handful of special-purpose registers. The general registers can be concatenated to handle 32-bit values. In a neat trick of multiplexing, the registers don’t even have to be combined in traditional even/odd pairs. You can use register r0 with r1, r1 with r2, or even r7 with r0. The address map is a flat 24-bit (16 MB) layout, which simplifies addressing and cuts down on segmentation tricks that x86 programmers have grown to hate. Instructions are a mixture of 16, 32, or 48 bits in length, and the instruction set itself is pretty standard, with the usual logical, arithmetic, and flow-control operations. Cambridge Consultants provides a set of gnu tools with every license.

One of XAP5’s little addressing tricks is designed to help execute-in-place from flash memory. All code and data are referenced relative to VBR, the processor’s vector base register. Simply changing the value in VBR changes the apparent location of your code and data without actually re-linking or upsetting any relative offsets. That, in turn, allows you to download code updates into an unused portion of flash memory, change VBR to point to it, and start executing the new code right away. Whether you erase the old code afterwards is up to you, but you won’t have to reboot the system or re-link all your subroutines or interrupt handlers. Simple, elegant, and practical.

XAP’s flash-centered design also helps it save power. Since code doesn’t have to be copied out of ROM at boot-up, you don’t have that power drain, or the attendant time delay.  You can put the chip to sleep and wake it up much more quickly. In fact, you can pull the plug entirely: XAP5 is a fully static design that doesn’t need to be clocked – or even have power – when it’s not being used. External interrupts could re-connect power (or at least, power-up the XAP5 portion of the ASIC), and the chip will be ready to handle the interrupt more or less instantaneously. For embedded systems that are idle or awaiting input most of the time, that’s a big-time power saver.

The hardware is well thought-out, even though XAP5 consumes only about 18,000 gates. An optional MMU is extra and offers the usual features of covering holes in the address map, relocating peripherals, catching illegal accesses, and so on. Depending on the feature set, the MMU can wind up bigger than the processor core.

Which leaves us with the software, the Achilles heel of most new processors. Designing a processor is comparatively easy; garnering third-party software support is hard. Although XAP has been around for years in its four earlier incarnations and has sold more copies than some Michael Jackson albums, it’s still not well supported by commercial tools. Apart from the free gnu tools, commercial compilers and RTOS ports are on the way, says Cambridge Consultants. For many developers, that’s not a significant drawback. For others, it’s a deal-breaker. Most embedded developers are more loyal to their software tools than they are to their microprocessor. They’ll choose a compiler or operating system first and the chip afterwards. Woe to any processor vendor that doesn’t support the customer’s chosen tools. You might as well be trying to sell a new religion.

In the end, XAP5’s ASIC-only implementation will automatically limit its appeal to well-heeled and fully staffed ASIC teams. Although XAP5 can be prototyped in an FPGA, it’s not really at home there, so there’s no way the average 10-person shop can include it in their project. Among ASIC developers, most are looking for top-notch support and mature tools. XAP5 has the former but not the latter. With time, XAP5’s software repertoire may broaden to include the top software hits. In the meantime, it’s a great little chunk of processor IP that works especially well in low-power, flash-based systems.

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