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New Kid in Class

Nios II Joins the Processor IP Race

He doesn’t just slip quietly into the back of the classroom.  He sits sideways in his desk, fidgets nervously, and makes the other kids ill-at-ease.  His classmates eye him cautiously.  He looks different, has a strange accent – maybe he even smells funny.  Back in his old school, he ruled the roost, but here, he’s got to fight his way up the popularity ladder from the very bottom.  A new kid is always a disruption to the class, even if he’s well behaved, mild mannered, and courteous.  An additional competitor disrupts the status-quo, and the arrival of the interloper immediately initiates a re-visiting of the pecking order. 

Altera and Synopsys announced an ASIC-optimized version of Altera’s Nios II processor architecture this week.  In the standard-cell ASIC arena, Nios is a newcomer.  Nios II is a 32-bit RISC architecture, not remarkably different from ARM or MIPS offerings, but it brings different advantages to the table that may have many engineering teams re-thinking their decision-making criteria for selecting a processor architecture.

In the “good old days” processors were picked on their own merits.  If you could deliver more performance, lower power consumption, or a superior instruction set, you stood a good chance of knocking out your rivals and winning the socket.  After awhile, however, design teams got more sophisticated.  The performance of the processor itself took a back seat to the development environment – the time and money you could save with robust development tools and a strong ecosystem outweighed the small (and temporary) advantages one processor might enjoy over another.

Then, we entered a new phase.  With the widespread adoption of open-source and architecture-independent development tools, previous experience and software IP took center stage as driving factors for adoption.  If your company was making a mobile phone, for example, the ecosystem support, legacy software library, and comprehensive IP portfolio made an ARM architecture a safe choice.  Ditto a MIPS architecture if your project was, say, a set-top box. 

Now, with the more widespread deployment of standardized operating systems and the proliferation of higher-level (and more portable) languages for software development, other factors become more important in the “which processor should we use?” decision.  This is where, perhaps, the upcoming offering from Altera and Synopsys has a chance to make some inroads.  Nios II won’t blow away the dominant architectures with blinding performance, miserly power consumption, low cost of deployment, or superior development tools.  It also will most certainly not crush the competition with a brimming bandwagon of existing adopters in any close-knit vertical market like mobile phones, set-top boxes, or DVD players. 

So – why would anyone choose Nios II for their next project?  The power of the Nios II story is in the adoption and development cycle itself.  Nios II has been a tremendously successful architecture for design teams using FPGAs to deploy embedded systems on chip.  When FPGAs first achieved the density and performance required to be a happy host to a full-fledged embedded computing system, Altera introduced Nios, a proprietary synthesizable processor architecture that could be reconfigured to anything from a tiny-footprint programmable state machine to a full-fledged (somewhat) high-performance embedded application software machine. 

Of course, if you planned to deploy your product someday in a form that made FPGA an impractical platform for cost or power reasons, you had to steer clear of FPGA-specific proprietary architectures like Nios.  You didn’t want to have to migrate to a completely different processor architecture (and port your entire base of software) if you went for cost reduction in an ASIC. 

To date, Altera’s solution to that dilemma has been what they call “HardCopy” – a program that allows a working FPGA design to be easily migrated to a metal-configured “structured ASIC” device with lower cost, higher performance, and much lower power consumption than its programmable counterpart.  HardCopy is an excellent option if your design goes only into mid-range production volume, if your power budget is modest but not miserly, and if your need for integration doesn’t surpass the gate count of the larger FPGAs. 

For products that hit still higher volumes, have aggressive power management requirements, or need to integrate in design blocks not available for FPGAs, however, Nios II was still off limits – until now.  The availability of an ASIC-optimized Nios II allows a design team to develop and prototype in an FPGA (or multiple FPGAs combined with other discrete parts and ASSPs), and then move to a fully-integrated, cost-reduced, power-pinching, performance-having ASIC after the design is stable, the volume is ramping, the early adopter customers have been satisfied, and the product is headed for margin land.

With FPGAs seeing dramatically increased use as prototyping and development platforms, the availability of a processor architecture that allows a smooth migration through all phases of the design and deployment process with no massive risk and discontinuity from a required port part way down the highway could be a godsend for many project teams.  You can start with a low-cost development board, click the mouse a few times in Altera’s SoPC (System on Programmable Chip) Builder tool, and literally in minutes have a ready-to roll hardware prototype of your embedded computing system that can be dropped on the desks of everyone in your embedded software team.  From there, you can continue to evolve both the hardware and software aspects of your product in parallel with absolute minimal cost and delay for each design iteration.  Once everything is right, you can easily migrate to the benefits of an ASIC-based solution on top of the exact same processor architecture.

This new kid may have something going for him.

Altera is smart enough to know that a line is not likely to form made up of people wanting to buy ASIC processor IP from an FPGA company.  To address this issue, they partnered with Synopsys – the number two supplier of ASIC IP (behind ARM) and the dominant supplier of just about everything besides processor IP.  This partnership makes great sense, as Synopsys is already well established with all the sales and support kinks worked out for the complicated IP market.

The specifics (like an actual processor data sheet for the ASIC version of Nios II or the actual available licensing models and cost) probably won’t be announced until sometime after the first of the year.  The two companies say the actual processor core will be available from Synopsys starting sometime in Q1 2008.  What the companies are saying, however, is that the offering has been driven by demand from existing Nios II users. (Altera says that over 20,000 Nios development kits have been deployed worldwide and claims that Nios II is the most popular FPGA processor, used in everything from flat-panel displays to industrial control systems.) 

They also say that the performance of the core will weigh in somewhere in the 500 DMIPS range using 90nm technology, compared with 228 DMIPS in 90nm versions of the HardCopy structured ASIC, 300 DMIPS in the latest 65nm Stratix III FPGAs (HardCopy structured ASIC for Stratix III is not yet announced), or 165 DMIPS in the 65nm low-cost Cyclone III FPGA platform.  This performance would put the processor on par with mid-range versions of the more established ARM and MIPS architectures on the same process technology.

The ASIC core will be less configurable than the FPGA version, allowing modification of instruction and data cache sizes, number and size of instruction and data TCMs, number of interrupt ports, and an optional hardware divider.  The core will be packaged as a standard Synopsys “coreKit” that uses the DesignWare coreConsultant utility to guide you through configuration, verification, and implementation.  The kit will include an RTL verification environment with ready-to-run tests and scripts for generating netlists and test vectors.

For Altera, it isn’t clear what the focus of the business strategy is for the ASIC version of Nios II.  If the company gets a significant chunk of licensing or royalty revenue, it might just be an IP business in itself.  Otherwise, perhaps they’re hoping that the continuous path from prototyping through cost-reduced ASIC will entice more design teams to start with Altera’s FPGAs rather than those from another supplier.  The answers to these questions will probably become clearer when the final announcement details roll out in early 2008.

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