“The translation of a conception, which was at the beginning, which is intended for ASIC in a FPGA, can poor and ineffective results give.”
So says the Google Translate tool, when offered the sentence:
“Translating a design that was originally intended for ASIC into an FPGA can yield poor and inefficient results.”
…and asked to translate from English to French to German and back to English. Google’s translation technology is actually very good – and the quality of these results is much higher than what we’d expect when, say, synthesizing a piece of ASIC IP into an FPGA. Get the picture? If you want a good quality, high-performance FPGA design, you need to create your register-transfer-level (RTL) description with a micro-architecture that is optimized for the coarse-grained architecture of FPGAs. Automatic mapping, while technically feasible, yields far from optimal results.
When designing a processor core, however, this is exactly the approach most people use – until now. Most processor IP was originally created for ASIC design and is carefully hand-optimized for best performance and area efficiency in an ASIC. When synthesizing those cores for FPGA, however, we often get pretty pathetic results.
ARM realized this and designed their new Cortex-M1 processor core specifically for FPGA implementation. As a result, we have a new processor that can be used in system-on-chip FPGAs that is far more efficient than typical ASIC cores synthesized into FPGA. ARM announced the new core this week in conjunction with Actel, who is licensing the core for use in their non-volatile FPGA families.
As FPGAs have grown in capability, large numbers of designers are looking at them as system-on-chip platforms for low- and medium-volume applications. When creating your system-on-chip, you will, of course need a processor. This is where the project gets sticky. FPGA companies, recognizing that ASIC processors don’t translate so well, have created their own new processor architectures (with which they’re more than happy to hook you up). The common problem with these processors is that (with the exception of Lattice Semiconductor’s open-source Mico32) they’re all proprietary. For some designers this isn’t an issue, but many others are faced with challenges like porting legacy embedded software onto a new processor and locking themselves into a particular silicon platform based on their processor choice.
ARM and Actel broke the proprietary FPGA processor mold back in 2005 with the introduction of their first collaborative effort – the CoreMP7 FPGA family with built-in license for ARM’s ARM7 processor core. The combination was very well received by the market, even though it still suffered from the Achilles heel of ASIC-to-FPGA inefficiencies.
Now they are partnering with the new Cortex-M1, delivering a solution with all the benefits of CoreMP7, but with a much more efficient core. The new core will become Actel’s smallest and highest performance 32-bit processor offering – a tribute to the ground-up FPGA-optimized architecture.
Many of the advantages of the new processor are obvious – design teams already accustomed to building systems with ARM processors will be right at home, and the existing ARM-enabled tools, peripherals, middleware, and software should all slide into the FPGA version quite handily. Cortex-M1 executes all existing Thumb code, uses the ARMv6-M instruction set, and is upward compatible with other Cortex processors. It uses the three-stage pipeline of the Cortex-M3 and operates up to 72 MHz in an Actel FPGA implementation. For talking with the rest of the world, it includes an AMBA AHB-lite interface and a separate external memory interface. Despite the impressive performance, it can be implemented in as few as 4300 tiles in an Actel device, yielding a much better performance-to-size ratio than previous FPGA-based processors.
As one would expect from a soft-core processor, Cortex-M1 is extremely configurable, featuring tightly-coupled memories that can be used for instruction or data in a variety of sizes, selectable fast or small multipliers, big- or little-endian operation, removable debug features, system timer, software interrupt, and a nested vector interrupt controller with 1-32 interrupts at 4 priority levels. You configure your processor core when you synthesize your RTL, so you can create a configuration that best matches your processing needs without taking extra chip overhead for capabilities you won’t use. Since FPGAs are re-programmable, you can experiment with this as your design progresses, making different tradeoffs and measuring performance in actual hardware.
Actel has a fairly complete set of tools to manage the FPGA and the platform-configuration side of things, and the immense ARM ecosystem brings along a gargantuan selection of compilers, debuggers, IDEs, RTOS, and other associated products from a variety of vendors. Actel’s free CoreConsole v1.3 supports the stitching together of your system on the FPGA via a graphical user interface. The system generates the Cortex-M1 as a black box in your synthesizable RTL, and then downstream tools plug in the actual implementation. Actel also supplies an Eclipse-based IDE that supports Cortex-M1 as well as their other FPGA-compatible processors.
The new processor can be used both in Actel’s M1Fusion family – a mixed-signal flash-based non-volatile FPGA architecture – and in Actel’s M1ProASIC3 flash-based non-volatile FPGA family. The core occupies about 30% of the largest Fusion device and about 20% of the largest ProASIC3 device, leaving plenty of hardware resources for the rest of your system-on-chip design.
ARM also plans to support other manufacturers’ FPGA families with the new core, and, ironically, that cross-vendor portability may work to Actel’s advantage as well. With most of the competitive processor cores locking you into a specific FPGA vendor’s products, an offering that promises easy migration to ASIC, to higher-performance ARM processors, and to other manufacturers’ FPGAs is a compelling reason to consider the ARM/Actel combination now.
From ARM’s perspective, the new core is a smart move because it positions the company well in the fast-emerging FPGA-based system market. It also offers existing ARM users a low-cost, flexible prototyping platform for designs that may ultimately find their way into higher-performance ASIC systems. Finally, it serves notice that the key players in the ASIC IP arena are not content to watch idly while FPGA companies monopolize the programmable-logic IP market with subsidized, proprietary cores.
The new core is scheduled for early access in Actel devices in Q2 2007, with early access to devices in Q3 and full product release in Q4.