We humans like to worry. Instead of being content with just living our happy lives, walking around enjoying the sunshine, eating our food, talking to each other on our mobile phones, and designing our next-generation electronic products, we mull and fuss about whatever nemesis might come along and end our little party. Will global warming overheat our junctions? Will earthquakes and volcanoes shake us into spilling our cocktails? Will comets and meteors crash into our spinning ball of fun, bringing on another ice age? With every additional year we speculate about new spoilers that might spell the end of our celebration.
IC technology is a bit like that too. With each passing process node, we predict the end of Mr. Moore’s prediction. Will this be the last shrink? What will finally stop the steaming semiconductor locomotive’s intrepid journey of exponential ecstasy? Will leakage current suck our power supplies dry? Will metal migration ruin our reliability? Will errant neutrons nail too many of our ground-level micro-transistors, sending us into single-event upsettedness? Every time the negative exponent on the dielectric dimensions grows larger, we strap on our sandwich boards and strut the streets shouting that the end is nigh.
FPGAs are on the point of that paranoic spear of semiconductor speculation. For the past several process generations, FPGAs have been the first complex devices to test the ropes on a new gate width, making them the prime subject of these prognosticators of process failure. As 90nm approached, we heard that leakage current would probably stop the show. FPGAs engaged in nothing more than holding onto their configurations would waste watts at such a frantic pace that practical use would be precluded by the countless coulombs coursing though their idle junctions. Nah. We were wrong.
90nm was more power efficient by most measures than any previous process node – just like all the process nodes before it. False alarm. Cancel the wake. Design in another family of fabulous FPGA technology and serve up another round of drinks. The demons of doom had spared us again. Low-K dielectrics, triple-oxides, improved design tools, and clever architectures had teamed up to defeat the inevitable, and we got two more years of wide open technology freeway to race down with our capability-hungry system designs.
65nm will be the end, though. Right? Surely something will upset our apple cart as we pass through the two-thirds of a tenth of a micron barrier. Will it be one of the usual suspects? Skyrocketing mask costs? Yield problems gone wild? Power, power, and more power? Evidently not.
Altera gave us a glimpse into their 65nm strategy this week, and it has power reduction written all over it. Citing a 65nm test chip program that goes back to 2003, Altera traced their progress through eight test chip iterations over a three year period, bringing them to Stratix III test devices working in the lab and at early customers today. While Stratix III is slated to be broadly available in 2007, there are interesting architectural details already starting to emerge.
It seems that power is the big boogeyman at 65nm, and Altera is taking significant steps to stop it in its tracks. Altera also claims to be reaping large rewards from redundancy technology introduced over a decade ago. This redundancy had a marginal effect in older generation technologies, but at 65nm it has the potential to dramatically improve yields. The yield gains come from salvaging a device by automatically deactivating a defective section and replacing it with a corresponding redundant section, much like the technology that has been in common use in memory devices for ages.
Despite the digital bias of FPGAs, there are analog aspects to deploying a new family as well, and it turns out that those are among the most difficult to debug and qualify during the process of generation hopping. “The digital logic scales well and tends to work predictably right out of the chute,” says David Greenfield, Sr. director of product marketing for high-density FPGAs at Altera. “The analog sections like PLLs and I/O are more challenging to characterize.” Altera walked us through their labs where they were evaluating jitter in PLLs, measuring signal integrity on I/Os operating at 2GHz, and conducting other characterizations on 65nm test parts.
Altera has been through the new process drill more than a few times, now, and their test chip methodology is well established. Each of the approximately ten planned test chip iterations brings up more complex capabilities than the last. Solutions and alternative approaches to problems identified in one round of test chips are fed into the next, so there is an orderly convergence on complex, working devices on a reasonably predictable schedule. Sometimes, several different architectures will be evaluated on a single piece of silicon, getting the most mileage out of each expensive fab turn.
With 65nm, though, despite the wide variety of challenges and difficulties involved in developing a new FPGA family, all eyes were on the power problem. Altera’s power priorities stem from a triple threat of effects related to the new process node, including the fact that doubling the density of the device would naturally double the power, increasing the clock frequency would raise the power consumption even more, and thinning the gate width would allow leakage current to increase, further jacking up the power by increasing static power consumption. None of these are good, of course, as future properties of devices that already have something of a dubious power reputation. Altera concluded that serious steps were required to bring power down. The trouble is, of course, that FPGAs are not amenable to many of the power reduction schemes typically employed on ASICs and other devices. They require their own bag of tricks.
The good news in power at 65nm is that dynamic power, the juice pulled by your device when it is doing real work, is reduced somewhat because of lower supply voltages. At 65nm our supplies have evidently dropped from 1.2V down to 1V. In order to further combat power, Altera has developed new logic cells that can operate at three different points in the performance/power tradeoff space. The new family will have a “High Performance” mode that uses about 30% less power than previous generation devices, a “Medium Performance” mode that uses about 50% less, and a “Low Performance” mode that sips up about 70% less power. They also have installed power-down modes in many of the parts of a design that might be completely inactive.
The theory is that your design can use the High Performance mode only in its critical timing paths and reduce overall power by backing the non-critical circuitry down to Medium and Low Performance modes. All this theory, of course, is no good unless you have some tools to help you turn on the right modes in the right place. In Altera’s study of customer designs, they found that only a small percentage of the logic, typically less than 20%, required the high-performance/high-power mode of operation. Altera has built automatic optimization into their design tool flow. As part of static timing analysis, paths are identified based on their slack as candidates for power reduction using the lower power modes.
Altera’s power-aware tools operate in three stages – synthesis works to minimize RAM accesses (which are infamous power hogs) and rearranges logic where possible to reduce the number of nets with high toggle-rates. Place and route identifies nets with high toggle rates and routes them for minimum capacitance. It also works to minimize clock power by its placement choices and tries to create power-efficient DSP block configurations. Finally, the assembler programs unused circuitry to minimize toggling. Altera’s Quartus tools also include a power optimization advisor that analyzes your design and offers tips for further reducing power consumption.
Altera claims that their overall power reduction strategy for the upcoming 65nm Stratix III line will achieve a total power reduction in the range of 50% from Stratix II for designs with comparable density and operating frequency, 70% reduction in total power for designs with 30% lower clock frequency (why we’d upgrade to a new generation device and slow down our design, we’re not quite sure) and a 30% reduction in total power for a design operating at 20% higher clock frequency (probably the most realistic scenario, since we engineers are always eager to hot-rod the new technology.)
If Altera’s power reduction measures are as effective as they predict, they should be off to the races with another highly competitive product family when 65nm FPGAs hit the mainstream. Meanwhile, with the power demons held at bay for another process generation, we doomsday prognosticators in the press and analyst community will have to conjure up new villains to cast in the semiconductor spoiler roles. What will it be next?
