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Mayday Mayhem

FPGA Announcements Galore

If March winds bring April showers, then April showers must somehow give rise to new announcements in programmable logic and structured ASIC. From tools to technology to applications, let’s sail through some of the most interesting announcements this week to pick up on the latest trends. There continue to be significant advances in the design tools, silicon technology, and applications for FPGAs and customizable logic devices. A close look at this week’s news serves to highlight the direction that the industry is currently taking.

As FPGAs continue their migration from glue logic devices to central components in complex systems, companies are responding with a wealth of new techniques and technologies to manage the challenges created by this new, starring role. This week, Altera introduced a new Quartus II with incremental compilation, Atmel rolled out a new line of FPGA-based platforms that facilitate function sharing, eASIC (along with STMicroelectronics) announced significant progress in proving its e-Beam personalized configurable fabric, Mentor Graphics made a major improvement in the design verification flow for users of its Catapult C, and Xilinx announced TS16949 certification of its XA family of FPGAs for automotive applications.

Altera’s Incremental Improvement

Altera announced version 5.0 of its Quartus II tools this week with an emphasis on “incrementality.” Every major software release has a wide range of improvements (and this Quartus II 5.0 is no exception), but incremental design is one that deserves special mention. As FPGAs have continued to grow larger and more complex, two trends have emerged that have presented special challenges for design tools. First, the “compile” time (the badly-named duration of a place-and-route run) has gone up significantly with recent generations of giant devices. What used to require a few minutes on your laptop can now take hours on a much faster machine. Second, the larger designs possible with larger devices often demand additional engineers. Many projects have gone beyond the one- or two-designer barrier and are having to deal with the implications of team-based design.

One way to combat long compile times and to better segment the design process between developers is to make the design process incremental in nature. In concept, you should be able to change only a section of your RTL design, and the affected steps of the design process such as synthesis, place-and-route, and timing analysis would only need to operate on the changed portions of the design, taking advantage of cached data for the sections of the project that were untouched. Unfortunately for FPGA and EDA vendors, this requires almost a complete bottom-up rework of the entire design tool flow. There is also a challenge posed by the dynamics of the incremental process itself, as sometimes the computational overhead associated with insuring the integrity of an incremental change marginalizes the benefits. There would be little point in making an incremental design change if the time required to run incrementally were as long as the time required for a complete rerun.

Altera claims about a 66% reduction in runtime, for an average incremental change compared with a complete rerun. Of course this will vary depending on the nature of the design, the size of the changed partition, and a number of other factors. An additional benefit of incremental compilation is improved design closure. If you’ve worked hard getting timing closure on some parts of your design, you don’t want to throw those parts back up to the mercy of a complete re-placement and re-routing just because you changed another unrelated block in your design. Incremental compilation allows you to implement changes in some parts of your circuit with minimal impact to other parts that need to remain stable.

Atmel’s Advantage

Atmel announced a new family of programmable-logic-based platforms called FPSLIC II that seek to increase the effective density and to decrease the cost and power consumption of FPGA-based designs by facilitating fast and easy reconfiguration for modal applications where several different functions can share the same silicon. With the convergence of functions like cameras, MP3 players, and phones into single devices, often one programmable device can be shared across multiple functions. Atmel has worked to make that silicon sharing easy to implement at both the tool and device level.

By sharing silicon, a smaller device can do the work of a much larger device, but with lower power consumption and smaller footprint. FPSLIC II includes a 25 MIPS, 8-bit AVR processor, 36KB of SRAM, a hard multiplier, peripherals, and FPGA fabric with 256 to 2300 cells. Atmel worked to make function swapping trouble-free by implementing a “virtual socket” in the FPGA fabric that can be populated by a variety of IP blocks, including peripherals, interfaces, and operators. At 25 MHz, reconfiguration of the device takes less than 9ms. All of the programming bitstreams are integrated into a single “master” bistream with memory pointers to individual functions.

eASIC Proves Potency

Working together with eASIC, STMicroelectronics has completed a 24-hour turnaround from RTL to tapeout for a 130nm ASIC containing eASIC’s eASICore. This demonstrates the flexibility that comes along with eASIC’s e-Beam customized fabric, which essentially bridges the gap between FPGA and ASIC. ST created a programmable printer platform containing a standard pre-verified printer engine combined with programmable eASIC fabric to allow customization of the printer controller and image processing. This allows the cost of a single ASIC to be shared among a number of variants, and those variants can be created and customized after the fact in a very short time by e-Beam customization of the eASIC fabric.

In a departure from both structured-ASIC and FPGA methodologies, eASIC has created a customizable fabric with FPGA-like look up tables (LUTs) as logic elements and customizable routing, programmed by e-Beam direct-write of a single via layer. Because the fabric is not mask customized, turnaround time is very short, and an entire wafer does not need to be dedicated to a single customization. Compared with FPGA customization, the technique produces higher density, higher performance and lower power consumption. Compared with mask-customized structured ASIC, it provides faster turnaround, lower NRE and smaller minimum quantities.

In addition to offering their fabric as a core for custom- and standard-cell designs, eASIC is expected to produce stand-alone devices featuring the technology in the future. The addition of the eASIC process provides another option in the growing constellation of solutions seeking to span the gap between FPGA and ASIC. Now, starting closest to FPGA implementation, we have Xilinx’s EasyPath, Altera’s HardCopy, eASIC’s direct-write e-Beam fabric, and a number of mask-customized structured ASIC options from companies such as AMI, chipX, Faraday, LSI Logic, NEC, and others. Each of these options provides different benefits and advantages in NRE, time-to-market, performance, power, density, IP availability, unit cost, packaging, and design tool flow.

Mentor’s Verification Victories

Mentor Graphics’s Catapult C created a buzz with its debut at last year’s Design Automation Conference (DAC) because of the credible and distinguished band of customers willing to stand up and vouch for the new product’s ability to create RTL directly from algorithmic ANSI C and C++ that rivaled and sometimes outperformed hand-crafted implementations. While this represented significant progress in algorithm-to-architecture synthesis technology, verification problems remained a substantial barrier to widespread adoption of the methodology.

This week, Mentor is announcing the addition of a new suite of verification capabilities inside Catapult C that help to bridge the verification gap between algorithms described in high-level languages like C and C++ and hardware architectures generated by their Catapult C synthesis tool. In addition to generating synthesizable RTL (HDL) from an untimed ANSI C/C++ algorithm, Catapult C now also generates additional models and transactors for system-level verification. Today, these include register-transfer level (RTL) models and cycle-accurate behavioral models in Verilog, VHDL, and System C. Mentor says that, by the second half of 2005, it will also produce timed, transaction-level models in SystemC. In addition to the new models, Catapult now generates SystemC wrappers called “transactors” that enable the connection of models at various levels of abstraction into a transaction-level verification environment.

What does all this accomplish? When you write your design starting in RTL, you create it with a specific cycle-by-cycle behavior in mind. You can then create a testbench to exercise and verify your design based on the expected cycle-accurate outputs. Starting from an untimed, behavioral level of abstraction, however, such as when designing in raw C and C++, there are many possible architectures that can implement any given high-level algorithm. Each of these architectures would have a different cycle-by-cycle behavior and would require a completely different RTL-level testbench.

Part of the power of high-level synthesis is the ability to try out different architectural implementations quickly, but manually creating a separate testbench for each architectural alternative would be far from quick. By wrapping transactors around models at various levels of abstraction, you can seamlessly substitute your models to achieve your goals for a particular verification run, whether you’re trying for maximum performance at a high level of abstraction or maximum detail at the RTL level. The simulation performance gains can be significant, as taking advantage of higher levels of abstraction can boost simulation performance by several orders of magnitude.

Xilinx’s Automotive Authority

Xilinx announced this week that they have achieved ISO/TS16949:2002 certification for their XA families of automotive FPGAs. If you don’t work in the automotive industry and are tempted to skip ahead in your reader, at least notice that this is further evidence of Xilinx’s increasing vertical market focus. As FPGAs spread into new markets, Xilinx seems to start from the customer side to create their marketing plans. Each time an important industry or application looks like a good fit for programmable logic solutions, Xilinx brings in expertise from inside that industry to help craft their strategy and define their marketing messages. As a result, they tend to be successful in speaking the technical language of the customers in that space, and it gives them a meaningful advantage independent of the capabilities of the silicon. Beyond that, it motivates them to seek out and clear the bar for industry-specific certifications and qualifications that will pave the way to market penetration in the new space.

In this case, Xilinx went for the relatively new TS16949 standard which is built on ISO9000:2001 and incorporates Italian, French, US, and German standards for automotive sector specific QMS requirements. Xilinx achieved the certification in 9 months and adds it to their suite of industry standards, which includes ISO9001, TL9000, QML, and ISO14001. The Xilinx XA family includes automotive versions of their Spartan-3, Spartan-IIE, CoolRunner, and 9500XL FPGA and CPLD families.

FPGA Fortune Telling

What do we read in all these technological tea leaves? First, notice that, in addition to assuming more important roles in system design, FPGAs are branching out dramatically in terms of the applications they address. In response to this diversity of applications, we are getting an increased number and variety of solutions. More and more platform devices are emerging that use some sort of configurable fabric along with optimized standard IP cores to address relatively narrow slices of the application space. We may be entering an era where FPGAs begin to give way to a new generation of domain-optimized platforms with various types of reconfigurable fabric that suit the specific needs of various design challenges. If this is true, watch for a rash of startups and new product lines aimed at specific application areas and a gradual decline in one-style-fits-all FPGA families.

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