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Considering the Total Cost of FPGAs

Field-programmable gate arrays (FPGAs) have a well-established position in every systems engineer’s toolbox. Taking advantage of their flexibility, engineers have used FPGAs for many years to rapidly prototype systems or in low-volume pre-production applications. When the communications- and network-driven Internet bubble took off at the turn of the millennium, demand skyrocketed for FPGAs in higher gate densities at any cost. Since then, however, FPGA requirements have changed dramatically. Today, as companies increasingly focus on the bottom line, engineers look for silicon solutions that offer both low unit and low total system cost. While ASICs have traditionally offered the lowest unit cost of any silicon solution at high volumes, escalating time-to-market pressures, exponentially increasing NRE charges and the rising need to mitigate risk are driving up ASIC unit costs, preventing them from addressing system designers’ needs.

Today, by leveraging advances in semiconductor process technology and ongoing manufacturing efficiencies, FPGA vendors are now able to offer programmable devices at unit costs comparable to traditional ASICs. In many highly cost-sensitive, or “value-based,” markets where FPGAs have not traditionally been widely used due to higher unit costs, FPGA-based solutions are now reaching a breakeven point with ASICs. In fact, analysts predict the use of FPGAs will continue to grow dramatically. With a CAGR of over 15 percent, analysts expect the overall programmable logic market will nearly triple in size between 2002 and 2008. Analysts also predict this growth will be driven by the rapid adoption of programmable logic within the automotive and consumer market segments. The use of FPGAs in consumer applications is forecast to grow to more than $1B by 2008, almost 10 times its 2002 revenue levels.

Defining User Needs

Given the high growth rates forecast for this market, FPGA vendors are aggressively positioning their technology as the best solution for these value-based applications. Many have begun promoting their products for the first time as low-cost ASIC alternatives. But, to successfully serve as an “ASIC alternative,” in the emerging value-based market, FPGAs must demonstrate not only low unit prices, but a total system cost structure that is highly competitive with ASIC unit costs plus their NRE.

FPGAs in this value market must match many of the additional characteristics that have made ASICs attractive in high-volume applications. The ASIC-like features that will factor heavily in the ASIC alternative decision-making process include: high performance, low power, security, reliability, live at power-up, single chip, small form factor, breadth of product offering and overall ease of use. It is important to note that with some FPGA technologies these additional capabilities are either not available or come at an additional cost. Accordingly, that added cost must be factored into the overall unit cost of the solution.

Technology Options

FPGA vendors offer two fundamental technologies in this value FPGA market segment: flash FPGAs, such as the Actel ProASIC3 families, and SRAM-based FPGAs offered by other vendors. At a glance, it is easy to assume that these two FPGA technologies offer similar characteristics and capabilities. Both are in-system programmable, offer high-performance programmable logic, and are available in densities to 1M system gates and beyond. In reality, however, there are very significant differences between the two technologies.

Like an ASIC, the nonvolatile nature of reprogrammable flash-based devices provides key advantages over the volatile SRAM-based offerings. Flash-based FPGAs use a flash programming cell to control the gate of the switch within the FPGA fabric. Each switch has a single sense gate (the switch) and a single flash floating gate that controls the state of the switch. In contrast, SRAM-based FPGAs rely on a six-transistor SRAM element for switch control and a pass gate for the switch itself. The volatile SRAM FPGA programming element must be loaded from an external device at every system power-up. Unlike SRAM-based devices, flash-based FPGAs are single chip and live at power-up, which allows for significant board-level cost savings.

From a system security standpoint, flash-based FPGAs are secure, immune from firm errors and can support secure remote updates over public networks. This higher level of security offers better protection against theft of critical IP. The device’s firm error immunity reduces the CEM’s risk of product liability and increases system reliability. The ability to conduct secure remote updates allows the product developer to update the product after deployment and, in the process, support a subscription-based business model through remote updates for feature enhancement. This capability can also eliminate the need for expensive service-based “truck rolls” to fix problems in the field.

Moreover, the inclusion of a small nonvolatile memory (NVM) in the flash devices can serve as an enabling technology in many consumer and automotive applications. The NVM can be used to store encryption keys for secure communications or to support device serialization in set-top boxes for broadcast-based systems.

Unit and System Cost Comparisons

A host of new FPGA products have recently entered the market touting never-before-seen unit costs. The ProASIC3 flash-based device from Actel for instance, starts at the industry’s lowest cost point — $1.50 (250K units). SRAM-based solutions are available for under $10 in two to three device densities, with a single device available at the sub-$5 ASIC-like price point.

In order to achieve these unit cost advantages, SRAM FPGA solutions must be implemented on the most aggressive process technologies. However, this aggressive use of process technology comes at the expense of total system cost. Designs using SRAM-based value FPGA solutions must add expensive board-level infrastructure to support the technology and, in the process undermine the cost competitiveness of the value SRAM FPGA.

FPGAs based on SRAM technology have always required additional support circuitry and value FPGAs are no different. Each SRAM-based FPGA requires a boot PROM or microcontroller to load the FPGA configuration data. To ensure system reliability, designers often add an SRAM power supply brown-out detection device. Moreover, many designs using SRAM-based FPGAs require a live at power-up CPLD (complex programmable logic device) to manage system start up, especially if a microcontroller is being used to load the SRAM FPGA.

SRAM-based FPGAs fabricated in the latest 90nm processes must also meet stringent specifications on power-up as well as tight power supply tolerances which often require costly supply sequencing devices to manage power to the part. In many applications, external clock distribution devices must handle system clock management because the SRAM FPGA’s power-up configuration delay makes the device’s internal PLL/DLL circuitry unsuitable for this important system-level task. In all, a SRAM-based FPGA may require anywhere from $3 to $20 of support circuitry. Accordingly, that additional cost must be factored in to determine the value SRAM-based FPGA’s true cost. The SRAM system overhead penalty can easily be over 100 percent of the SRAM FPGA’s unit cost price without looking at the soft costs of reliability, inventory management and design complexity issues.

In contrast, the cost savings of using flash-based FPGAs extends well beyond unit cost. The ASIC-like single chip, live at power-up nature of flash-based FPGAs allows designers to eliminate the additional devices associated with the SRAM FPGA. Unlike SRAM-based FPGAs, flash-based devices offer a true ASIC-like approach to the board-level design. For example, flash-based devices support single (1.5V) power supply-based designs, which eliminate the need for additional voltage regulators. These devices power-up and down in a controlled and predictable way. Since they are inherently low power, the devices reduce power supply requirements, enhance system reliability and lower system thermal management costs. By supporting the use of separate power pins (same voltage) to inputs and outputs, flash-based FPGAs reduce noise and may contribute to reduced EMI emissions. Additionally, by reducing component count, they help designers minimize PCB board size.


Technology constantly changes to meet the needs of the marketplace. Over the past 10 years, flash technology has rapidly evolved from an innovative idea into a disruptive technology, dramatically impacting every application it has touched. It has transformed cell phones, cameras, video recorders, simple PLDs, microcontrollers and memory solutions into revolutionary variants of their predecessors. Today flash technology is poised to do the same for the programmable logic market. By transforming the basic cost structure of FPGAs, it promises to bring the flexibility and rapid deployment advantages of programmable logic to the value-based market.

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