If you want to minimize the power consumption of your system, you can’t wait until you have your design reduced to gates. Yeah, you can do some things there to help, but the big wins come earlier, at the architectural or RTL levels.
But how do you know at that point how much current your design will draw? In particular, dynamic current? Past approaches have used average activity rates or some such general number to give a squint-your-eye approximation, but it’s hard to get that number right, and it’s harder to … Read More → "Detailed RTL Power Analysis"