June 2015 – EEJournal

Detailed RTL Power Analysis

June 18, 2015

If you want to minimize the power consumption of your system, you can’t wait until you have your design reduced to gates. Yeah, you can do some things there to help, but the big wins come earlier, at the architectural or RTL levels.

But how do you know at that point how much current your design will draw? In particular, dynamic current? Past approaches have used average activity rates or some such general number to give a squint-your-eye approximation, but it’s hard to get that number right, and it’s harder to … Read More → "Detailed RTL Power Analysis"

Apple Hints at CPU Change

by Kevin Morris

June 18, 2015

One of the many things to come out of Apple’s recent Worldwide Developers’ Conference (WWDC) last week was an almost offhand discussion of something called Bitcode. It’s an intermediate software format, neither source code nor binary code. And its existence suggests that Apple is getting ready to change its microprocessor architecture. Otherwise, what’s the point?

Bitcode is not the first or only time that software companies have used intermediate formats to make apps hardware-independant. It’s not even the first time Apple has done it. But it does suggest that the Cupertino firm is … Read More → "Apple Hints at CPU Change"

Ayla’s Mobile App Platform

by Kevin Morris

June 16, 2015

Baking is more of a science than other types of cooking. Cakes can be particularly tricky to get just right when it comes to structure and texture. Skilled bakers can assemble an amazing cake from bare ingredients, but your average household cook or baker may find that more difficult. Instead, they can purchase cake mixes, with all the ingredients included in the right proportions. They just add a few key liquid ingredients, mix, bake, … Read More → "Ayla’s Mobile App Platform"

New Toy in the Sandpit

by Dick Selwood

June 12, 2015

EDA Playground is a neat idea. From your browser you can simulate chunks of SystemVerilog, Verilog, VHDL, C++, SystemC and other HDLs, using Aldec and Cadence tools. The idea is you can learn about the tools, evaluate and share code, develop and share small prototypes, and generally have a fun time – if playing with EDA design is your idea of fun. And it is free.

Now EDA training company, Doulos, which acquired EDA Playground earlier this year, is adding Synopsys’ VCS verification tool providing another dimension to the Playground.

The EDA Playground was the … Read More → "New Toy in the Sandpit"

The Essence of Big Data

by Dick Selwood

June 11, 2015

The biggest buzzword that every press release must reference in the title these days is “Internet of Things” (IoT). The second biggest buzzword would appear to be “Big Data”. (Although the IoT uses Big Data, resulting in a re-entrant ranking problem that’s too much for my brain after two conferences this week.)

The question I’ve struggled with, however, is, & … Read More → "The Essence of Big Data"

Benchmarks for IoT Edge Nodes

by Bryon Moyer

June 2, 2015

If you’ve been in the market for microprocessor benchmarks, then you’re probably familiar with EEMBC. Their most recent benchmark suite, ULPbench, was designed to compare microcontrollers (MCUs) so that purchasers could get a neutral, apples-to-apples view of which MCUs consume the least energy.

That’s all fine and good, but it also establishes a path towards something similar but more inclusive: Internet-of-Things (IoT) edge nodes. These are the units way at the edge of the IoT that fundamentally do three things: measure something, do some minor computation, and then send the data… somewhere. Usually wirelessly.</ … Read More → "Benchmarks for IoT Edge Nodes"