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Rumors Intel Altera Deal is Close

The NY Post reported today that sources told them that an Intel/Altera deal was close, and could be done by the end of next week.

At the same time, we are hearing from multiple Altera customers who are opposed to the deal. The customers are concerned that Intel would shift Altera’s focus away from meeting their needs, and that Intel is poorly equipped to run an FPGA business – which is almost more of a software and service business than a “chip” business.

Key concerns surround Altera’s highly-capable AE resources who are viewed … Read More → "Rumors Intel Altera Deal is Close"

Is Exactly-Once Delivery Possible with MQTT?

We looked at MQTT, along with various other messaging protocols, not too long ago. Included in the discussion was a brief mention of MQTT having quality-of-service (QoS) features – and one of those is debatable.

MQTT’s optional QoS levels are to guarantee delivery no more than once (in which case you may miss a message), at least once (in which case you might get a duplicate), or exactly once. This latter one is the subject of debate: various threads in various … Read More → "Is Exactly-Once Delivery Possible with MQTT?"

Differentiating Your IoT Widget – in Hardware

iStock_000019503663_Medium.jpgWhat does it take to be successful as a maker of an Internet-of-Things (IoT) edge-node product? This question doesn’t have an obvious answer, partly because there are many contributors to success. But in a discussion with Open Silicon at the recent IoT DevCon, it became clear to me that taking their view into account makes for two opposing forces – forces they’re trying to unify.

On the one side, there … Read More → "Differentiating Your IoT Widget – in Hardware"

Cadence’s Faster Debug Idea

Cadence is proposing a new way to approach debug. It’s almost an obvious way, except that this isn’t how most debug has traditionally been done. The real reason this hasn’t been done before is simple: data. We’ll come back to that in a sec.

Their point is that, for most debug today, you have to anticipate where problems are likely to crop up and then manually instrument your code with “printf” statements (or the equivalent) so that you get some visibility into what’s going on … Read More → "Cadence’s Faster Debug Idea"

Faster NoC Tuning

In a sleepy little town of 4 or 5 houses, you can be pretty informal about how mail arrives at its destinations. People can come pick it up at the post office, or the postmaster can drop it off on the way home, or whatever works. But once you get too many houses, you have to get organized: create routes and schedules and hire delivery folks to handle deliveries in a more structured manner.

That’s what’s happened with SoCs: the ad-hoc interconnect schemes of yore are giving way to networks-on-chip (NoCs) so that the complex … Read More → "Faster NoC Tuning"

Intel/Altera Agreement (Partially) Tells the Tale

We did a lot of speculation in our recent articles about the rumored Intel bid to buy Altera. One of the areas of most intense speculation was the 2013 agreement the two companies signed – for Intel to manufacture 14nm FPGAs for Altera.

More than two years after that deal was signed, Intel is rumored to be making an offer to buy Altera for upwards (maybe far upwards) of $10B. But, is the existing 2013 agreement potentially weakening Intel’s bargaining position?

The key parts of the agreement that we thought could be … Read More → "Intel/Altera Agreement (Partially) Tells the Tale"

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