editor's blog
Subscribe Now

Wide-Ranging Approaches to Ranging

As I’ve mentioned before, there are constants at ISSCC (e.g., sessions on image processing and sensors) and then there are the circuits-of-the-month. Ranging seemed to be one of the latter, showing up in both image-processing and sensor sessions. So I thought I’d summarize some of the widely differing approaches to solving issues related to ranging for a variety of applications.

For those of you following along in the proceedings, these come from sessions 7 and 12.

Session 7.4 (Shizuoka University, Brookman Technology) offered a background-cancelling pixel that can determine the distance of an object using time-of-flight (ToF). As you may recall, ToF is more or less like light radar (LIDAR?) where the arrival of the reflection of a known emitted light gives you the distance.

There are four lateral gates in this pixel, directing charge from impinging light into one of three floating diffusion areas (the fourth gate simply discharges the pixel).

Background cancellation has historically been done by comparing adjacent frames, but quick motion can create strange artifacts. So at the beginning of the capture cycle for this work, the background is measured and stored in the first diffusion for subtraction. Then the emitter turns on and collection moves to the second diffusion. The reflection may also return during that time; when the emitter shuts off, then collection changes to the third diffusion. The difference between those two charge amounts gives the distance.

Session 7.5 (Shisuoka University) addresses the challenge of doing high-precision ranging for the purposes of, say, modeling an object. The problem is that, to get higher resolution, you ordinarily need to separate the light source from the imager by a wide angle. That’s hard to do in a small device. Such devices typically have resolution in the few-cm range, which isn’t much use for object modeling; this work achieved 0.3-mm resolution.

The keys were three:

  • They use an extremely short (< 1 ns) light pulse.
  • They used a drain-only modulator (DOM) – by eliminating the lateral pass gate, they get a faster response. The pixel itself can only accumulate or drain.
  • They capture all of the pixels at once, but the tight timing brings another issue: skew between pixels is no longer noise, but can screw up the measurement. So they implemented a column deskew circuit and procedure.

Microsoft weight in in Session 7.6 (they couldn’t help putting a flashy brand on their opening slide – something that you generally don’t see at ISSCC, but I guess the expert marketing guys from SEO Slack need something to prove their value, even if it meant being tasteless). This was an improved Kinect ranging system where the challenge is in accommodating both distant low-reflectivity (i.e., low-light) and close-in high-reflectivity (i.e., high-light) objects. Pretty much your classic dynamic range issue complicated by the distance thing.

They have decoupled the collection of charge in a floating diffusion and an “A or B” assignment that will be used to calculate the distance. They use A and B rows as inputs to a differential cell. A high-frequency clock alternates A and B activation during collection; this means that the assignment to A or B, determined by the clock, happens simultaneously with charge collection. The transfer to a floating diffusion can then happen afterwards, at a leisurely pace (to use their word).

They also implemented a common-mode reset to neutralize a bright ambient. And each pixel can set its gain and shutter time; this is how they accommodate the wide dynamic range.

Meanwhile, over in Session 12, folks are using other sensors for ranging. In Session 12.1 (UC Berkeley, UC Davis, Chirp Microsystems), they built a pMUT (piezoelectric micro-machined ultrasonic transducer) array to enable gesture recognition. Think of it as phased-array radar on a miniscule scale. They process the received signals by phase-shifting – basically, beamforming – in an attached FPGA.

Within the array, some pMUTs (think of them as ultrasonic pixels, sort of) are actuated to send a signal, others listen to receive the reflection, and some do both. They can decide which of these to do for optimization purposes on a given application.

They also want to sample at 16x the resonant frequency of the sensors to lower in-band quantization noise and simplify the cap sizing. (No relation to an unfortunate boating incident.) But that means they need to know the actual, not approximate, resonant frequency for a given device – natural variation has to be accommodated, as does response to changing environmental conditions like temperature.

To do this, they have a calibration step where they actuate the sensors and measure their ring-down, using the detected frequency to set the drive frequency of the actuator. This calibration isn’t done with each capture; it can be done once per second or minute, as conditions for a given application warrant.

As always, the details on these sessions are in the proceedings.

Leave a Reply

featured blogs
Dec 5, 2023
Introduction PCIe (Peripheral Component Interconnect Express) is a high-speed serial interconnect that is widely used in consumer and server applications. Over generations, PCIe has undergone diversified changes, spread across transaction, data link and physical layers. The l...
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at intel.com/leap. The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines.

Read more

featured chalk talk

Portenta C33
Sponsored by Mouser Electronics and Arduino and Renesas
In this episode of Chalk Talk, Marta Barbero from Arduino, Robert Nolf from Renesas, and Amelia Dalton explore how the Portenta C33 module can help you develop cost-effective, real-time applications. They also examine how the Arduino ecosystem supports innovation throughout the development lifecycle and the benefits that the RA6M5 microcontroller from Renesas brings to this solution.  
Nov 8, 2023
3,202 views