editor's blog
Subscribe Now

Power Bank SoCs

I ask a lot of stupid questions because usually they’re not stupid. Occasionally one is.

OK, maybe not outright stupid, but I certainly felt out of the loop. I was talking with Active-Semi about their new power bank management chips. But I tend to run my phones with minimal bells and whistles on. WiFi is typically off; GPS is often off. Bottom line: the charge on my phone can easily last a day, sometimes two.

So I hope I can be forgiven for not knowing in advance what a “power bank” was. I’ve never had a chance to need one. Apparently I’m not typical: Active-Semi’s Mark Cieri noted that it’s not unusual for smartphones to need a new charge after only 4 hours. Who knew… (Apparently everyone but me!)

Active-Semi has announced two new SoCs for managing these critters. As they describe it, the status quo requires separate components: a power path chip, a linear charger, a buck/boost regulator, and a microcontroller to manage it all.

Their solution is a single chip that integrates all of these capabilities together, including management and regulation. One version delivers 1 A; the other 2.1 A. The result: a noticeably (50%) smaller footprint.

Oh, and significantly less power draw: under 10 µA, vs. 45 – 100 µA for conventional circuits. So the manager won’t be siphoning off too much of the energy it’s supposed to be managing.

You can find out more in their announcement.

Leave a Reply

featured blogs
Apr 16, 2024
The accelerated innovations in semiconductor design have raised customers' expectations of getting smaller, faster, high-quality SoCs at lower costs. However, as a result, the SoC designs are getting complex, resulting in intricate design simulations and explosive data g...
Apr 16, 2024
Learn what IR Drop is, explore the chip design tools and techniques involved in power network analysis, and see how it accelerates the IC design flow.The post Leveraging Early Power Network Analysis to Accelerate Chip Design appeared first on Chip Design....
Mar 30, 2024
Join me on a brief stream-of-consciousness tour to see what it's like to live inside (what I laughingly call) my mind...

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured chalk talk

Shift Left with Calibre
In this episode of Chalk Talk, Amelia Dalton and David Abercrombie from Siemens investigate the details of Calibre’s shift-left strategy. They take a closer look at how the tools and techniques in this design tool suite can help reduce signoff iterations and time to tapeout while also increasing design quality.
Nov 27, 2023
19,047 views