We’ve talked about Breker’s C-level test generation tools a couple of times in the past. But the context for that discussion was simulation – the tests were run in the virtual domain.

But not all validation happens there. There are several scenarios where hardware platforms contribute to the verification plan. Emulators are one good example, where programmable hardware elements implement newly-designed logic so that extensive testing that might be too slow for simulation – in particular, running software – can be performed.

Likewise, FPGA prototypes can be part of the plan. These are usually faster than an emulator implementation, but they take longer to create since they’re optimized for speed. They’re often used by software writers as a way to test software that will ultimately run on the silicon chip. But such software designers may well be interested in stressing the design with specific uses cases that their software may exercise. So some of the silicon verification can bleed over to them.

Finally, after all of the verification is done, you have an actual chip. (With all the focus on 100%-proof-that-it-works before cutting masks, it’s easy to forget that we’re actually making a real chip.) That chip must be validated to ensure that it works the way the verification plan said it would.

All of these scenarios are now supported by Breker’s TrekSoC-Si product, which complements the existing version. It means that tests generated for simulation can also be applied in all of these other phases of verification and validation.

You can find out more in their release.