editor's blog
Subscribe Now

Triple Patterning Explosion

The type of patterning to be used at a given technology node is determined layer-by-layer. At 10 nm, SADP is planned for metals, but contacts are looking like they’ll require triple patterning, according to Mentor’s David Abercrombie.

We’ve talked about LELE coloring before, and algorithms exist to automatically color a circuit with linear scaling – twice as big a circuit takes twice as long to color. But when you go to LELELE, it’s no longer linear: it’s np-complete. Beyond 30 features to be colored, the algorithm isn’t going to finish in a lifetime.

So coloring algorithms are instead being approached using heuristics and constraints. For instance, it’s generally considered better to balance the colors so that there are roughly the same number of features on each color. That eliminates all of the gazillion possible decompositions that don’t meet that criterion.

There is also some concern that different decompositions might have different litho effects. It’s not known yet whether this will be an issue, but that would certainly complicate matters, since the algorithm would now have to take lithographic distortions into effect – as if it didn’t already have enough to think about.

Leave a Reply

featured blogs
Oct 23, 2020
Processing a component onto a PCB used to be fairly straightforward. Through hole products, a single or double row surface mount with a larger center-line rarely offer unique challenges obtaining a proper solder joint. However, as electronics continue to get smaller and conne...
Oct 23, 2020
[From the last episode: We noted that some inventions, like in-memory compute, aren'€™t intuitive, being driven instead by the math.] We have one more addition to add to our in-memory compute system. Remember that, when we use a regular memory, what goes in is an address '...
Oct 23, 2020
Any suggestions for a 4x4 keypad in which the keys aren'€™t wobbly and you don'€™t have to strike a key dead center for it to make contact?...
Oct 23, 2020
At 11:10am Korean time this morning, Cadence's Elias Fallon delivered one of the keynotes at ISOCC (International System On Chip Conference). It was titled EDA and Machine Learning: The Next Leap... [[ Click on the title to access the full blog on the Cadence Community ...

featured video

Demo: Low-Power Machine Learning Inference with DesignWare ARC EM9D Processor IP

Sponsored by Synopsys

Applications that require sensing on a continuous basis are always on and often battery operated. In this video, the low-power ARC EM9D Processors run a handwriting character recognition neural network graph to infer the letter that is written.

Click here for more information about DesignWare ARC EM9D / EM11D Processors

featured paper

Designing highly efficient, powerful and fast EV charging stations

Sponsored by Texas Instruments

Scaling the necessary power for fast EV charging stations can be challenging. One solution is to use modular power converters stacked in parallel. Learn more in our technical article.

Click here to download the technical article

Featured Chalk Talk

Mom, I Have a Digital Twin? Now You Tell Me?

Sponsored by Cadence Design Systems

Today, one engineer’s “system” is another engineer’s “component.” The complexity of system-level design has skyrocketed with the new wave of intelligent systems. In this world, optimizing electronic system designs requires digital twins, shifting left, virtual platforms, and emulation to sort everything out. In this episode of Chalk Talk, Amelia Dalton chats with Frank Schirrmeister of Cadence Design Systems about system-level optimization.

Click here for more information