editor's blog
Subscribe Now

What Is “Good” Yield?

In a recent piece on antenna tuning, I addressed circuit and MEMS approaches, and one of the advantages of circuits was said to be better yield. So I contacted the MEMS folks in that space for their comments on yield, and I received a carefully-worded comment from Cavendish Kinetics (and none from WiSpry).

I interpreted the Cavendish comment as basically acknowledging that yields weren’t great but were on a typical learning curve. Well, it turns out that interpreting the comments as saying yield is good or bad depends on what standard you hold for “good” yield.

I had a follow-up conversation with Cavendish Kinetics’ Larry Morrell, who had provided the yield comment. The purpose of the conversation was to address their technology more generally (which we’ll cover in the future), but the yield topic cropped up. Apparently my interpretation of Larry’s comments had caused some… heartburn.

So, while this was spurred by this particular exchange, it raises a more general question: What should “typical” expected yields be? If you’re talking about MEMS, according to Larry, you might expect in the 40-60% range. So being on a typical learning curve that tops out at such numbers would suggest yields at or below the 40% range.

But not all MEMS suppliers are in that range. For instance, InvenSense does wafer-level bonding between a MEMS wafer and an ASIC wafer. Because they don’t rely on known-good dice, their overall yield will be a product of the MEMS and ASIC yields. They’ll be throwing away any good ASICs that happen to mate up with a faulty MEMS die and vice versa. So such a strategy works only if yields are high for both the MEMS and the ASIC. And a quick conversation with an InvenSense representative at a show last year suggested their yields are in the 90%+ ranges.

Cavendish Kinetics also says their yields are in the 90% range. So why the cautious words? Because they’re not using “typical” MEMS yields as their standard; they’re using CMOS yields as their standard, and those should be well into the 90s. So having around 90% yield isn’t good enough; they’re still working up the curve. In fact, looking back at Larry’s words, he does say “…normal yield learning curve for a CMOS process.” I just interpreted that to mean the shape, not necessarily the absolute values.

Going forward, it suggests that standards could be changing. Companies scoring in the 90s will increasingly put pressure on lower-yielding companies if they meet in the market. That last qualifier is important, since there are many MEMS companies that address very specific niche markets where there is little competition and where pricing isn’t so deadly. As long as no 90%ers dive in to compete, they’re OK. But they should certainly have their radar out…

Leave a Reply

featured blogs
Oct 14, 2019
Simon Segars opened Arm TechCon with a new look, having discovered that real men have beards. This is the 15th Arm TechCon. In this post I'm going to focus on the new things that Arm announced... [[ Click on the title to access the full blog on the Cadence Community sit...
Oct 13, 2019
In part 3 of this blog series we looked at what typically is the longest stage in designing a PCB Routing and net tuning.  In part 4 we will finish the design process by looking at planes, and some miscellaneous items that may be required in some designs. Planes Figure 8...
Oct 11, 2019
The FPGA (or ACAP) universe gathered at the San Jose Fairmount last week during the Xilinx Developer Forum. Engineers, data scientists, analysts, distributors, alliance partners and more came to learn about the latest hardware, software and system level solutions from Xilinx....
Oct 11, 2019
Have you ever stayed awake at night pondering palindromic digital clock posers?...
Oct 11, 2019
[From the last episode: We looked at subroutines in computer programs.] We saw a couple weeks ago that some memories are big, but slow (flash memory). Others are fast, but not so big '€“ and they'€™re power-hungry to boot (SRAM). This sets up an interesting problem. When ...