editor's blog
Subscribe Now

Simpler CDC Exception Handling

For static timing analysis, it’s a concept that goes back years. You get a bunch of violations, and then you have to decide which ones represent false paths or multi-cycle paths and create “exceptions” for them. Tedious.

Well, apparently formal analysis can have the same issue. Only here they’re referred to as “waivers,” according to Real Intent. If you run analysis and get a long list of potential violations, you have to go through the list and, one by one, check them for “false positives” and mark them as such. Time-consuming and error-prone. And tedious. Especially when working on large-scale SoCs (so-called “giga-scale”).

In their latest release of Meridian CDC, which does clock-domain crossing verification, Real Intent has provided a different way of handling this: provide more granular control over the run parameters in the form of rules or constraints that can be successively refined.

Using the old method, if a particular over-reaching aspect of analysis caused 100 false positives, you’d have to find all 100 and “waive” them. With the new approach, when you find the first one, you make the refinement, and then, with a rerun of the analysis, the one you found and the other 99 all disappear. OK, not disappear per se, but they’re grouped together as not being an unexpected finding. You can also review that list to make sure nothing snuck through. (This is a simplification of a more sophisticated overall process, but it captures the essence.)

This may take some iterations, but in the end, you can have a clean run with no exceptions, and the way you got there is less likely to have involved a mistake here or there.

You can find out more about Real Intent’s latest Meridian CDC release in their announcement.

Leave a Reply

featured blogs
Jan 17, 2022
Today's interview features Dajana Danilovic, an application engineer based near Munich, Germany. In this video, Dajana shares about her pathway to becoming an engineer, as well as the importance of... [[ Click on the title to access the full blog on the Cadence Community sit...
Jan 13, 2022
See what's behind the boom in AI applications and explore the advanced AI chip design tools and strategies enabling AI SoCs for HPC, healthcare, and more. The post The Ins and Outs of AI Chip Design appeared first on From Silicon To Software....
Jan 12, 2022
In addition to sporting a powerful processor and supporting Bluetooth wireless communications, Seeed's XIAO BLE Sense also boasts a microphone and a 6DOF IMU....

featured video

Synopsys & Samtec: Successful 112G PAM-4 System Interoperability

Sponsored by Synopsys

This Supercomputing Conference demo shows a seamless interoperability between Synopsys' DesignWare 112G Ethernet PHY IP and Samtec's NovaRay IO and cable assembly. The demo shows excellent performance, BER at 1e-08 and total insertion loss of 37dB. Synopsys and Samtec are enabling the industry with a complete 112G PAM-4 system, which is essential for high-performance computing.

Click here for more information about DesignWare Ethernet IP Solutions

featured paper

How an SoM accelerates and simplifies processor-based designs

Sponsored by Texas Instruments

If you're comfortable working with integrated circuits that have four to 48 pins, building a custom printed circuit board (PCB) for a new product might make sense. But when your design is complex—think: processor with more than 300 pins, DDR memory, eMMC, complex physical layout, and all the electrical considerations that go with it—a simpler, lower-risk, off-the-shelf product is often a better solution. Discover the benefits of a system-on-module (SoM) for complex, high-pin-count PCB designs.

Click here to read more

featured chalk talk

Accelerating Physical Verification Productivity Part Two

Sponsored by Synopsys

Physical verification of IC designs at today’s advanced process nodes requires an immense amount of processing power. But, getting your design and verification tools to take full advantage of the compute resources available can be a challenge. In this episode of Chalk Talk, Amelia Dalton chats with Manoz Palaparthi of Synopsys about dramatically improving the performance of your physical verification process. 

Click here for more information about Physical Verification using IC Validator