editor's blog
Subscribe Now

The Scribe and the Princess and the Pea

OK, perhaps “scribe line” is more accurate, but I do love a double entendre (even if not salacious). I had a discussion with KLA-Tencor at SPIE Litho recently regarding two new machines they’ve just announced. The first allows detection of defects through spectral analysis. The issue it faces is that it relies on test structures in the scribe line, which are facing two challenges: more of them are needed and there’s less space.

More test features are required both because of new structures like the FinFET and new processing steps, double-patterning in particular. But such structures have taken advantage of a generous scribe line area, dictated originally by the width or kerf of actual mechanical saws way back in the day. The cutting is done by laser now, so the kerf is no longer the issue. The scribe line is actually having a measurable impact on dice per wafer, so shrink it must.

The features that their SpectraShape 9000 analyzer looks for are periodic, and their spectra when illuminated by broadband light can be analyzed twelve ways from Sunday. Each of those features goes in a “box” that is currently 45 µm square. To accommodate the smaller scribe line, they’ve reduced the box size to 25 µm on a side (meaning they can almost put four of them where one of the old ones would have gone).

This has come with higher broadband light power, improved sensitivity, and higher throughput for more sampling.

Meanwhile, we’ve come to the point where the smallest (OK, maybe not smallest, but very small) particle – on the backside of the wafer – can push the upper surface out of the depth of field during exposure. Seriously. Total princess-and-pea situation. It gets worse because smaller particles tend to stick harder due to van der Waals forces. And yet such a particle may transfer to the chuck, sharing the donation with the next wafers to come through.

Rather than noticing the effect of such a particle and then going and figuring out where it is, they’ve created a new use model: inspect the backside.* Of each wafer, before it goes into a process. This prevents the particles from ever getting into the chamber – as long as it can be done quickly enough to keep the line moving.

They’ve boosted sensitivity on their BDR300 by 10x to allow for detection of half-micron defects at 100 wafers/hour. They also have a review capability, allowing inspection of defects down to 0.2 µm. It can be integrated into their CIRCL cluster.

You can find out more about these machines in their release.

 

 

*There’s so much potential for abusing this… especially when looking for defects like paddle marks… but this is a family newspaper. Oh, OK, who am I kidding…

Leave a Reply

featured blogs
Dec 1, 2022
Raspberry Pi are known for providing lost-cost computing around the world. Their computers have been used by schools, small businesses, and even government call centers. One of their missions is to educate children about computers and to help them realize their potential thro...
Nov 30, 2022
By Chris Clark, Senior Manager, Synopsys Automotive Group The post How Software-Defined Vehicles Expand the Automotive Revenue Stream appeared first on From Silicon To Software....
Nov 30, 2022
By Joe Davis Sponsored by France's ElectroniqueS magazine, the Electrons d'Or Award program identifies the most innovative products of the… ...
Nov 18, 2022
This bodacious beauty is better equipped than my car, with 360-degree collision avoidance sensors, party lights, and a backup camera, to name but a few....

featured video

Maximizing Power Savings During Chip Implementation with Dynamic Refresh of Vectors

Sponsored by Synopsys

Drive power optimization with actual workloads and continually refresh vectors at each step of chip implementation for maximum power savings.

Learn more about Energy-Efficient SoC Solutions

featured paper

Algorithm Verification with FPGAs and ASICs

Sponsored by MathWorks

Developing new FPGA and ASIC designs involves implementing new algorithms, which presents challenges for verification for algorithm developers, hardware designers, and verification engineers. This eBook explores different aspects of hardware design verification and how you can use MATLAB and Simulink to reduce development effort and improve the quality of end products.

Click here to read more

featured chalk talk

EdgeLock® Secure Element & Secure Authenticator

Sponsored by Mouser Electronics and NXP Semiconductors

Today’s IoT designs demand comprehensive security implementation, but incorporating a robust security solution in your design can be a complicated and time-consuming process. In this episode of Chalk Talk, Amelia Dalton and Antje Schutz from NXP explore NXP’s EdgeLock Secure Element and Secure Authenticator Solution. They examine how this flexible, future-proof and easy to deploy solution can be a great fit for a variety of IoT designs.

Click here for more information about NXP Semiconductors EdgeLock® SE050 Plug & Trust Secure Element Family