editor's blog
Subscribe Now

3D-IC Planning

During Cadence’s recent CDNlive event, I had a discussion with Kevin Rinebold to talk about 3D-IC planning and design. Actually, it’s more than that, covering all of the multi-die/package combinations like system-in-package (SiP), complex PC boards, and interposer-based solutions. The basic issue is that it’s becoming increasingly difficult to separate die design from board/package design; you may have to plan both together.

Said another way, what used to be board design duties have encroached on die design as packages have started to look more and more like micro-PCBs. The “lumpiness” of old-fashioned design is giving way to a more distributed approach as the “lumps” interact in non-lumpy ways.

Cadence’s approach splits the process in two: planning and implementation. Their focus during our discussion was the planning portion. Why split this part of the process out? Because it’s generally being done by the packaging people (“OSATs”), not the silicon people. So the OSATs will do high-level planning – akin to floorplanning on a die (and may actually involve floorplanning on a substrate).

They hand their results to the implementation folks via an abstract file and, possibly, some constraints to ensure that critical concerns will be properly addressed during design. The abstract file isn’t a view into a database; it is a one-off file, so if changes are made to the plan, new abstracts can (or should) be generated.

Cadence says the key to this is their OrbitIO tool, from their Sigrity group. It allows mechanical planning – things like ensuring that power and ground pins are located near their respective planes. They can also do some power IR drop analysis, although more complete electrical capabilities will come in the future.

There’s one other reason why the planning and implementation are done with completely different tools (mediated by the abstract file): OSATs tend to work on Windows machines, while designers tend to work on Linux machines. No, this is not an invitation to debate. (Oh, wait, Apple isn’t involved in this comparison… OK… never mind…)

Leave a Reply

featured blogs
Jul 10, 2020
[From the last episode: We looked at the convolution that defines the CNNs that are so popular for machine vision applications.] This week we'€™re going to do some more math, although, in this case, it won'€™t be as obscure and bizarre as convolution '€“ and yet we will...
Jul 10, 2020
I need a problem that lends itself to being solved using a genetic algorithm; also, one whose evolving results can be displayed on my 12 x 12 ping pong ball array....
Jul 9, 2020
It happens all the time. We'€™re online with a designer and we'€™re looking at a connector in our picture search. He says '€œI need a connector that looks just like this one, but '€¦'€ and then he goes on to explain something he needs that'€™s unique to his desig...

featured video

Product Update: High-Performance DesignWare Memory Interface IP

Sponsored by Synopsys

Get the latest update on Synopsys' DesignWare Memory Interface IP for DDR5, LPDDR5, and HBM2/2E and how you can enable your DRAMs with the highest-performance, lowest-power, and lowest-area IP solution.

Click here to learn more about Synopsys' DesignWare Memory Interface IP for DDR5, LPDDR5, and HBM2/2E

Featured Chalk Talk

Prototyping Billion-Gate Designs with Protium X1 Enterprise Prototyping System

Sponsored by Cadence Design Systems

FPGA-based Prototyping certainly isn’t new. And our needs for early firmware and software development, memory modeling and advanced data capture haven’t gotten any better, if anything - they have gotten worse. Hi, I’m Amelia Dalton - host of Chalk Talk. Today my Juergen Jaeger from Cadence Design Systems and I are talking about the next generation of FPGA-based prototyping and how the first Scalable, Data Center-Optimized Enterprise Prototyping System can get your system design up and running faster than ever before.

Click here for more information about Protium X1 Enterprise Prototyping Platform