editor's blog
Subscribe Now

3D-IC Planning

During Cadence’s recent CDNlive event, I had a discussion with Kevin Rinebold to talk about 3D-IC planning and design. Actually, it’s more than that, covering all of the multi-die/package combinations like system-in-package (SiP), complex PC boards, and interposer-based solutions. The basic issue is that it’s becoming increasingly difficult to separate die design from board/package design; you may have to plan both together.

Said another way, what used to be board design duties have encroached on die design as packages have started to look more and more like micro-PCBs. The “lumpiness” of old-fashioned design is giving way to a more distributed approach as the “lumps” interact in non-lumpy ways.

Cadence’s approach splits the process in two: planning and implementation. Their focus during our discussion was the planning portion. Why split this part of the process out? Because it’s generally being done by the packaging people (“OSATs”), not the silicon people. So the OSATs will do high-level planning – akin to floorplanning on a die (and may actually involve floorplanning on a substrate).

They hand their results to the implementation folks via an abstract file and, possibly, some constraints to ensure that critical concerns will be properly addressed during design. The abstract file isn’t a view into a database; it is a one-off file, so if changes are made to the plan, new abstracts can (or should) be generated.

Cadence says the key to this is their OrbitIO tool, from their Sigrity group. It allows mechanical planning – things like ensuring that power and ground pins are located near their respective planes. They can also do some power IR drop analysis, although more complete electrical capabilities will come in the future.

There’s one other reason why the planning and implementation are done with completely different tools (mediated by the abstract file): OSATs tend to work on Windows machines, while designers tend to work on Linux machines. No, this is not an invitation to debate. (Oh, wait, Apple isn’t involved in this comparison… OK… never mind…)

Leave a Reply

featured blogs
Dec 1, 2023
Why is Design for Testability (DFT) crucial for VLSI (Very Large Scale Integration) design? Keeping testability in mind when developing a chip makes it simpler to find structural flaws in the chip and make necessary design corrections before the product is shipped to users. T...
Nov 27, 2023
See how we're harnessing generative AI throughout our suite of EDA tools with Synopsys.AI Copilot, the world's first GenAI capability for chip design.The post Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

TDK CLT32 power inductors for ADAS and AD power management

Sponsored by TDK

Review the top 3 FAQs (Frequently Asked Questions) regarding TDK’s CLT32 power inductors. Learn why these tiny power inductors address the most demanding reliability challenges of ADAS and AD power management.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at intel.com/leap. The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines.

Read more

featured chalk talk

Electrical Connectors for Hermetically Sealed Applications
Many hermetic chambers today require electrical pathways to provide internal equipment with power, data or signals, or to receive data and signals from equipment within the chamber. In this episode of Chalk Talk, Amelia Dalton and Brad Taras from Cinch Connectivity Solutions explore the role that seals and connectors play in the performance of hermetic chambers. They examine the methodologies to determine hermetic seal leaks, the benefits of epoxy hermetic seals, and how Cinch Connectivity’s epoxy-based seals and hermetic connectors can add value to your next design.
Aug 22, 2023
12,162 views