editor's blog
Subscribe Now

3D-IC Planning

During Cadence’s recent CDNlive event, I had a discussion with Kevin Rinebold to talk about 3D-IC planning and design. Actually, it’s more than that, covering all of the multi-die/package combinations like system-in-package (SiP), complex PC boards, and interposer-based solutions. The basic issue is that it’s becoming increasingly difficult to separate die design from board/package design; you may have to plan both together.

Said another way, what used to be board design duties have encroached on die design as packages have started to look more and more like micro-PCBs. The “lumpiness” of old-fashioned design is giving way to a more distributed approach as the “lumps” interact in non-lumpy ways.

Cadence’s approach splits the process in two: planning and implementation. Their focus during our discussion was the planning portion. Why split this part of the process out? Because it’s generally being done by the packaging people (“OSATs”), not the silicon people. So the OSATs will do high-level planning – akin to floorplanning on a die (and may actually involve floorplanning on a substrate).

They hand their results to the implementation folks via an abstract file and, possibly, some constraints to ensure that critical concerns will be properly addressed during design. The abstract file isn’t a view into a database; it is a one-off file, so if changes are made to the plan, new abstracts can (or should) be generated.

Cadence says the key to this is their OrbitIO tool, from their Sigrity group. It allows mechanical planning – things like ensuring that power and ground pins are located near their respective planes. They can also do some power IR drop analysis, although more complete electrical capabilities will come in the future.

There’s one other reason why the planning and implementation are done with completely different tools (mediated by the abstract file): OSATs tend to work on Windows machines, while designers tend to work on Linux machines. No, this is not an invitation to debate. (Oh, wait, Apple isn’t involved in this comparison… OK… never mind…)

Leave a Reply

featured blogs
Sep 16, 2021
I was quite happy with the static platform I'd created for my pseudo robot heads, and then some mad impetuous fool suggested servos. Oh no! Here we go again......
Sep 16, 2021
CadenceLIVE, Cadence's annual user conference, has been a great platform for Cadence technology users, developers, and industry experts to connect, share ideas and best practices solve design... [[ Click on the title to access the full blog on the Cadence Community site. ]]...
Sep 15, 2021
Learn how chiplets form the basis of multi-die HPC processor architectures, fueling modern HPC applications and scaling performance & power beyond Moore's Law. The post What's Driving the Demand for Chiplets? appeared first on From Silicon To Software....
Aug 5, 2021
Megh Computing's Video Analytics Solution (VAS) portfolio implements a flexible and scalable video analytics pipeline consisting of the following elements: Video Ingestion Video Transformation Object Detection and Inference Video Analytics Visualization   Because Megh's ...

featured video

Maxim Integrated is now part of Analog Devices

Sponsored by Maxim Integrated (now part of Analog Devices)

What if we didn’t wait around for the amazing inventions of tomorrow – and got busy creating them today?

See What If: analog.com/Maxim

featured paper

Choose a high CMTI gate driver that cuts your SiC switch dead-time

Sponsored by Maxim Integrated (now part of Analog Devices)

As GaN and SiC FETs begin to replace MOSFET and IGBT technologies in power switching applications, this Maxim paper discusses the key considerations when selecting an isolated gate driver. The paper explains the importance of CMTI and propagation delay skew and presents an isolated gate driver IC ideal for use with these new power transistors.

Click to read more

featured chalk talk

Just 1-Wire to Power and Operate I2C or SPI Endpoints

Sponsored by Mouser Electronics and Maxim Integrated (now part of Analog Devices)

If you are working on a connection or IO constrained design, a one wire solution could be a great way for you to power and operate your I2C or SPI endpoints. In this episode of Chalk Talk, Amelia Dalton chats with Scott Jones from Maxim Integrated about the DS28E18 communications bridge: a one wire solution that can help you address a variety of system level challenges including protocol conversion, wiring limitations, and communication distance concerns.

Click here for more information about the Maxim Integrated DS28E18EVKIT Evaluation System