editor's blog
Subscribe Now

Tools vs IP

All of the major EDA companies have had IP. Synopsys started with DesignWare before IP was a real concept; Mentor had IP associated with consulting for several years; Cadence has made a couple of acquisitions – notably memory – to bolster its internal IP efforts.

But the early products of these groups were typically lower-level IP – particularly I/O protocols. Not having to plough through hundreds of pages of a complex protocol spec was an attractive thing – assuming you were willing to trust your vendor to get it right or you had some way of verifying it without having to learn it yourself. And assuming you were willing to pay for IP (not a given in the early days).

Meanwhile, increasingly sophisticated IP from IP companies increasingly requires an accompanying tool to help configure the IP and integrate it with the rest of the design.

So we’ve had tools companies making IP; IP companies making tools.

And the IP part of the EDA play has become far more visible, almost holding its own against the tools themselves. And more and more, a robust IP portfolio is seen as including a processor. Intel/AMD and ARM obviously have their own well-established franchises (of which only ARM is an IP play), but there have been a few other notable players. MIPS was a recognizable contender, even if it never managed to outpace its archrival ARM; it was recently gobbled up by Imagination Technologies.

There has remained another processor company still duking it out with its own unique story. Tensilica promised a configurable processor. In essence, you told the tools what you wanted to do, and, in the end, you got a processor tailored for your application. And the software tools to compile to it.

Well, Tensilica is now betrothed to Cadence. My colleague Jim Turley noted the parallel to Synopsys’s purchase of ARC. Didn’t notice that one? Yeah, that’s because Synopsys bought Virage bought ARC*. And ARC also boasted configurability, and had a focus on the audio business – a space that Tensilica has participated in.

So we have the continued agglomeration of IP and EDA together. Dominated by ARM, followed by Two of the Big Three EDA guys. And Imagination.

Now we have more tools guys making IP; fewer IP guys making tools.

Some discussion today with Cadence reveals a bit more nuance. There’s debate as to whether a Tensilica core really competes with an ARM core. The customizability of the Tensilica core for very specific vertical applications means it gets more deeply embedded, often running with no OS at all. In fact, it is marketed as a data plane, suggesting the need for an accompanying control plane host. Some even say it’s an alternative to RTL, not an alternative to ARM.

Meanwhile, Cadence is promoting a theme of “next-generation IP” that, at first blush, sounds just like what IP has always been. The concept is that you can’t really count on shrink-wrapped IP that’s reusable by all comers. Each customer is going to want specific changes and adaptations that no one else may want (or that they want to keep to themselves).

This has always been the case – to the point where the on-the-shelf IP has historically been a teaser to engage in a consulting contract to give the customer what they actually want. So why is this suddenly a “next generation” thing?

The difference is that this customization is intended to be automated. In other words, the IP base is built with numerous knobs, and a tool accomplishes the customization per the knobs that the customer wants tuned. In fact, it intentionally starts to look more like a tool – a circuit generator – than a piece of circuitry. This has obviously been happening already here and there; it was central to what Tensilica was doing.

So we’ll have a tool guy making IP that looks like a tool.

You can see more about the merger in their release

 

 

 

*And ARC bought Teja Technologies, an event that rendered This Then-Intrepid-Marketing-Exec to explore an opportunity to be This Intrepid Reporter…

Leave a Reply

featured blogs
Oct 19, 2020
Have you ever wondered if there may another world hidden behind the facade of the one we know and love? If so, would you like to go there for a visit?...
Oct 19, 2020
Sometimes, you attend an event and it feels like you are present at the start of a new era that will change some aspect of the technology industry. Of course, things don't change overnight. One... [[ Click on the title to access the full blog on the Cadence Community si...
Oct 16, 2020
Another event popular in the tech event circuit is PCI-SIG® DevCon. While DevCon events are usually in-person around the globe, this year, like so many others events, PCI-SIG DevCon is going virtual. PCI-SIG DevCons are members-driven events that provide an opportunity to le...
Oct 16, 2020
[From the last episode: We put together many of the ideas we'€™ve been describing to show the basics of how in-memory compute works.] I'€™m going to take a sec for some commentary before we continue with the last few steps of in-memory compute. The whole point of this web...

Featured Paper

Four Ways to Improve Verification Performance and Throughput

Sponsored by Cadence Design Systems

Learn how to address your growing verification needs. Hear how Cadence Xcelium™ Logic Simulation improves your design’s performance and throughput: improving single-core engine performance, leveraging multi-core simulation, new features, and machine learning-optimized regression technology for up to 5X faster regressions.

Click here for more information about Xcelium Logic Simulation

featured paper

Fundamentals of Precision ADC Noise Analysis

Sponsored by Texas Instruments

Build your knowledge of noise performance with high-resolution delta-sigma ADCs. This e-book covers types of ADC noise, how other components contribute noise to the system, and how these noise sources interact with each other.

Click here to download the whitepaper

Featured Chalk Talk

SLX FPGA: Accelerate the Journey from C/C++ to FPGA

Sponsored by Silexica

High-level synthesis (HLS) brings incredible power to FPGA design. But harnessing the full power of HLS with FPGAs can be difficult even for the most experienced engineering teams. In this episode of Chalk Talk, Amelia Dalton chats with Jordon Inkeles of Silexica about using the SLX FPGA tool to truly harness the power of HLS with FPGAs, getting better results faster - regardless of whether you are approaching from the hardware or software domain.

More information about SLX FPGA