editor's blog
Subscribe Now

20-nm Test Enhancements

ITC is usually the time when the EDA companies announce their coolest test-related advances. While Mentor announced their IJTAG support, Synopsys focused its agenda largely on the issues surrounding the 20-nm node. Each node has its particular failure modes, and tests need to be added or refocused to catch those failures.

Two of the advances they announced involved memory and multicore; we’ll take them in order.

They first announced a change to their STAR memory system, both adding and removing hierarchy. The architecture of their memory test has been made hierarchical, with an SMS Server at the top that is connected to one or more chains of SMS Processors. Each processor handles several individual memory blocks. Cache and other high-speed memory associated with higher-end cores can also be mapped to a test bus that is managed by an SMS Processor.

Where hierarchy was taken away was in the wrapping of the memory blocks. Regardless of the type of memory, there’s a wrapper to interface it to the SMS Processor. But a true wrapper adds a level of hierarchy, and this can wreak havoc with constraints and such. So what they’ve done is keep the wrapper at the same hierarchical level as the memory. Which makes it more of a shim than a wrapper.

On the multicore side of things, they have shared pins to allow concurrent testing of multiple cores. Each core has its own internal test compression, and if all of the cores are identical, then ATPG can create a set of patterns that all cores can test concurrently. If the cores aren’t identical (but similar), then the ATPG handles one of the cores, and then goes to the other cores to see what was fortuitously covered by the vectors already created; it can then create supplementary vectors to patch any other coverage holes. Those extra vectors will have no impact on the cores already fully covered.

Of course, this raises the question, if you’re testing these all in parallel and one fails, how will you know which one? They have more than one output, and by looking at the outputs along with the patterns, they can positively ID where the issue was.

This sharing of the test pins (note that it’s not muxing the pins, it’s literally sharing) reduces both the test time and the number of pins required.

These are some of the highlights of what they announced; you can find more in their release.

Leave a Reply

featured blogs
Apr 24, 2019
In this week's Whiteboard Wednesdays video, Industry expert Rohit Kapur introduces the basic concepts of digital IC scan compression. Topics explained include the impacts of test application time... [[ Click on the title to access the full blog on the Cadence Community ...
Apr 23, 2019
Samtec Bulls Eye® test point systems are ideal for high-performance test applications because of their compression interfaces, small footprint, and high cycle count capabilities. Bulls Eye is now available in 50 GHz and 20 GHz designs, with a system up to 70 GHz in developme...
Apr 23, 2019
Move over, Information Age'€”the Autonomous Age is on its way. In the autonomous age, information is not just copious and accessible, it is integrated into our daily lives to automatically augment human capabilities. In the autonomous age, we expect technology to comprehend...
Jan 25, 2019
Let'€™s face it: We'€™re addicted to SRAM. It'€™s big, it'€™s power-hungry, but it'€™s fast. And no matter how much we complain about it, we still use it. Because we don'€™t have anything better in the mainstream yet. We'€™ve looked at attempts to improve conven...