editor's blog
Subscribe Now

What’s New at 20 nm

We talked in a separate piece today about Synopsys’s multi-source clock synthesis technology, but that was only one of several pieces of new technology in their new package. Among other parts of the release were the following non-trivial items:

  • Double patterning: it’s real now. It’s not used for every layer, just the bottom few layers. But it’s no longer something that will come someday: it’s here.
  • In the past, metal was metal. When routing, each layer was useful, and all layers were considered to be the same. That’s not the case anymore: lower layers have skinny, resistive lines; upper layers have broader, less-resistive lines. So now it matters which layer gets used. If the router is going to pick a layer, it has to consider the performance implications.
  • IP blocks are standard today. The problem is, they don’t usually fit together particularly well, leaving narrow routing channels that tend to get congested. They’ve improved their router so that it restricts that area only to signals that really need to be there; everything else is routed a different way to make the best use of that limited space.

You can find a brief discussion about what’s new for 20 nm in IC Compiler can be found in their release announcing their work with Renesas; and what’s new in their other tools is outlined briefly in their release announcing their work with Samsung.

Leave a Reply

featured blogs
May 24, 2022
Today is going to be my monthly update. This normally runs on the last Friday of the month, but that's a Cadence Global Recharge Day, so we will all be off. For various other reasons, I need to... ...
May 20, 2022
I'm very happy with my new OMTech 40W CO2 laser engraver/cutter, but only because the folks from Makers Local 256 helped me get it up and running....
May 19, 2022
Learn about the AI chip design breakthroughs and case studies discussed at SNUG Silicon Valley 2022, including autonomous PPA optimization using DSO.ai. The post Key Highlights from SNUG 2022: AI Is Fast Forwarding Chip Design appeared first on From Silicon To Software....
May 12, 2022
By Shelly Stalnaker Every year, the editors of Elektronik in Germany compile a list of the most interesting and innovative… ...

featured video

EdgeQ Creates Big Connections with a Small Chip

Sponsored by Cadence Design Systems

Find out how EdgeQ delivered the world’s first 5G base station on a chip using Cadence’s logic simulation, digital implementation, timing and power signoff, synthesis, and physical verification signoff tools.

Click here for more information

featured paper

5 common Hall-effect sensor myths

Sponsored by Texas Instruments

Hall-effect sensors can be used in a variety of automotive and industrial systems. Higher system performance requirements created the need for improved accuracy and more integration – extending the use of Hall-effect sensors. Read this article to learn about common Hall-effect sensor misconceptions and see how these sensors can be used in real-world applications.

Click to read more

featured chalk talk

KISSLING Products: Rugged and Reliable Solutions

Sponsored by Mouser Electronics and TE Connectivity

Rugged and reliable designs today have a specific set of design requirements that may not be found in other industries including robustness, durability, and the ability to resist harsh environments. In this episode of Chalk Talk, Amelia Dalton chats with Mark Dickson from TE Connectivity about the KISSLING product family which includes a wide variety of rugged and reliable solutions for your next design.

Click here for more information about TE Connectivity / KISSLING Ruggedized Switching Products