editor's blog
Subscribe Now

What’s New at 20 nm

We talked in a separate piece today about Synopsys’s multi-source clock synthesis technology, but that was only one of several pieces of new technology in their new package. Among other parts of the release were the following non-trivial items:

  • Double patterning: it’s real now. It’s not used for every layer, just the bottom few layers. But it’s no longer something that will come someday: it’s here.
  • In the past, metal was metal. When routing, each layer was useful, and all layers were considered to be the same. That’s not the case anymore: lower layers have skinny, resistive lines; upper layers have broader, less-resistive lines. So now it matters which layer gets used. If the router is going to pick a layer, it has to consider the performance implications.
  • IP blocks are standard today. The problem is, they don’t usually fit together particularly well, leaving narrow routing channels that tend to get congested. They’ve improved their router so that it restricts that area only to signals that really need to be there; everything else is routed a different way to make the best use of that limited space.

You can find a brief discussion about what’s new for 20 nm in IC Compiler can be found in their release announcing their work with Renesas; and what’s new in their other tools is outlined briefly in their release announcing their work with Samsung.

Leave a Reply

featured blogs
Aug 1, 2021
https://youtu.be/I0AYf5V_irg Made in Long Ridge Open Space Preserve (camera Carey Guo) Monday: HOT CHIPS 2021 Preview Tuesday: Designed with Cadence Video Series Wednesday: July Update Thursday:... [[ Click on the title to access the full blog on the Cadence Community site. ...
Jul 30, 2021
You can't attack what you can't see, and cloaking technology for devices on Ethernet LANs is merely one of many protection layers implemented in Q-Net Security's Q-Box to protect networked devices and transaction between these devices from cyberattacks. Other security technol...
Jul 29, 2021
Learn why SoC emulation is the next frontier for power system optimization, helping chip designers shift power verification left in the SoC design flow. The post Why Wait Days for Results? The Next Frontier for Power Verification appeared first on From Silicon To Software....
Jul 28, 2021
Here's a sticky problem. What if the entire Earth was instantaneously replaced with an equal volume of closely packed, but uncompressed blueberries?...

featured video

Accelerate Intelligent SLAM with DesignWare ARC EV Processor IP

Sponsored by Synopsys

Simultaneous localization and mapping (SLAM) algorithms build a map and determine location in the map at the same time. But how can you speed up the results? This demo shows how ARC EV processor IP with CNN engine accelerates KudanSLAM algorithms.

Click here for more information about DesignWare ARC EV Processors for Embedded Vision

featured paper

Harnessing the Power of Data to Enhance Quality of Life for Seniors

Sponsored by Maxim Integrated

This customer testimonial highlights the CarePredict digital health platform. Its main device, the Tempo wearable, uses artificial intelligence to derive actionable insights to enhance care and quality of life for seniors.

Click to read more

featured chalk talk

Software and Automotive Safety

Sponsored by Siemens Digital Industries Software

In the realm of automotive designs, safety must reign above all else. But the question remains: How can we innovate within the constraints of today’s safety standards? In this episode of Chalk Talk, Amelia Dalton chats with Rob Bates from Siemens about the role ISO 26262 plays when it comes to COTS and open source software, what certified software components are all about, and how heterogeneous multiprocessing can be helpful in your next automotive design.

Click here to download the whitepaper called "Is it Possible to know how Safe we are in a World of Autonomous Cars?