editor's blog
Subscribe Now

Tying Up the Missing Link

Methodics’s ProjectIC platform is intended to help manage large design projects by keeping the numerous different files associated with the design (so-called “views” – the unbranded sort, whose branded counterpart we’ll discuss in a couple days) in sync with each other. These may include RTL source files, schematic views, analysis runs, layout, and other design artifacts. They’re tied to each other by dependencies that Methodics builds.

One thing they haven’t had completely covered is test. They’ve handled analog test, but not digital. This was the motivation of their recent purchase of Missing Link, which, in particular, has a design management infrastructure that includes digital test and regression.

So Methodics will now be building in the dependencies to those artifacts as well. You can find more detail on the companies in their press release.

Leave a Reply

featured blogs
Oct 27, 2021
ASIC hardware verification is a complex process; explore key challenges and bug hunting, debug, and SoC verification solutions to satisfy sign-off requirements. The post The Quest for Bugs: The Key Challenges appeared first on From Silicon To Software....
Oct 27, 2021
Cadence was recently ranked #7 on Newsweek's Most Loved Workplaces list for 2021 and #17 on Fortune's World's Best Workplaces list. Cadence received top recognition among thousands of other companies... [[ Click on the title to access the full blog on the Cadence Community s...
Oct 20, 2021
I've seen a lot of things in my time, but I don't think I was ready to see a robot that can walk, fly, ride a skateboard, and balance on a slackline....
Oct 4, 2021
The latest version of Intel® Quartus® Prime software version 21.3 has been released. It introduces many new intuitive features and improvements that make it easier to design with Intel® FPGAs, including the new Intel® Agilex'„¢ FPGAs. These new features and improvements...

featured video

DesignCon 2021 112G Ethernet & PCIe 6.0 IP Demos

Sponsored by Synopsys

This video features Synopsys' silicon-proven DesignWare 112G Ethernet and PCIe 6.0 PHY IP solutions successfully interoperating with Samtec's AI/ML edge connectors and Amphenol's Direct Attach Copper (DAC) cables with superior Bit Error Rates (BERs) at maximum performance.

Click here for more information about DesignWare 112G Ethernet PHY IP

featured paper

Voltage Balancing Techniques for Series Supercapacitor Connections

Sponsored by Maxim Integrated (now part of Analog Devices)

For applications where supercapacitors need to be charged to more than 2.5V or 2.7V, engineers are forced to connect multiple supercapacitors in a series. This application note reviews the voltage balancing techniques in series supercapacitor connections for Maxim’s MAX38886/MAX38888/MAX38889 backup regulators.

Click to read more

featured chalk talk

Traveo II Microcontrollers for Automotive Solutions

Sponsored by Mouser Electronics and Infineon

Today’s automotive designs are more complicated than ever, with a slew of safety requirements, internal memory considerations, and complicated power issues to consider. In this episode of Chalk Talk, Amelia Dalton chats with Marcelo Williams Silva from Infineon about the Traveo™ II Microcontrollers that deal with all of these automotive-related challenges with ease. Amelia and Marcelo take a closer look at how the power efficiency, smart IO signal paths, and over the air firmware updates included with this new MCU family will make all the time-saving difference in your next automotive design.

Click here for more information about Cypress Semiconductor Traveo™ II 32-bit Arm Automotive MCUs