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Tying Up the Missing Link

Methodics’s ProjectIC platform is intended to help manage large design projects by keeping the numerous different files associated with the design (so-called “views” – the unbranded sort, whose branded counterpart we’ll discuss in a couple days) in sync with each other. These may include RTL source files, schematic views, analysis runs, layout, and other design artifacts. They’re tied to each other by dependencies that Methodics builds.

One thing they haven’t had completely covered is test. They’ve handled analog test, but not digital. This was the motivation of their recent purchase of Missing Link, which, in particular, has a design management infrastructure that includes digital test and regression.

So Methodics will now be building in the dependencies to those artifacts as well. You can find more detail on the companies in their press release.

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"Scalable Power Delivery" for High-Performance ASICs, SoCs, and xPUs

Sponsored by Infineon

Today’s AI and Networking applications are driving an exponential increase in compute power. When it comes to scaling power for these kinds of applications with next generation chipsets, we need to keep in mind package size constraints, dynamic current balancing, and output capacitance. In this episode of Chalk Talk, Mark Rodrigues from Infineon joins Amelia Dalton to discuss the system design challenges with increasing power density for next generation chipsets, the benefits that phase paralleling brings to the table, and why Infineon’s best in class transient performance with XDP architecture and Trans Inductor Voltage Regulator can help power  your next high performance ASIC, SoC or xPU design.

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