editor's blog
Subscribe Now

Validating Serial Protocols

When I was approached to talk about a new product from Arasan, I ran afoul of my favorite source of confusion from the Bureau of Arbitrary Definitions: I thought it was a verification story, when in fact it’s a validation story.

In case you think those two sound like pretty much the same thing, I always like to reinforce the confusion by defining verification as the act of proving that your design is a valid implementation of the design spec, while validation is the act of verifying that your design works properly in its desired setting. (Confused more? You’re welcome.)

Most of what we discuss in these pages is verification – making sure that there are no implementation deviations from the design spec. We spend much less time on validation, where the design is put into its native operating environment to see if it works as intended. This is often the domain of emulators, where you can connect in real system components or drive in real data traffic at speed to see how things work.

Arasan notes that this is becoming a problem with protocol stacks that communicate across gigabit (and higher) serial links – the emulators can’t keep up. They might be able to handle the physical layer (for instance, if there are FPGAs in the emulator, it’s likely they can handle serial data), but even so, the higher level portions of the protocol stack will be emulated, meaning they can’t run at speed.

They say that the standard solution for this is to place a rate-matching unit between the emulator and whatever is being used to validate the design. But because the emulator is slow, you end up waiting a lot – it certainly doesn’t reflect what a real traffic pattern would look like. In addition, apparently not all protocols have a rate-matching solution: MIPI, for example, can’t be handled that way.

So Arasan has released what is essentially a small tester that can be connected to a high-speed prototype board to test the design without an intervening rate matcher. It has a processor that handles the top levels of the protocol stack; that’s then shipped over to an FPGA that handles the bottom 4 levels of the stack and drives out directly to the design you’re testing.

They have different connectivity boards that can be swapped out for different protocols. Yes, in theory you could combine them, but they say that it’s rare that a design team needs to validate more than one protocol: a specific connection will operate on only one.

You can find more information in their press release

Leave a Reply

featured blogs
Dec 8, 2023
Read the technical brief to learn about Mixed-Order Mesh Curving using Cadence Fidelity Pointwise. When performing numerical simulations on complex systems, discretization schemes are necessary for the governing equations and geometry. In computational fluid dynamics (CFD) si...
Dec 7, 2023
Explore the different memory technologies at the heart of AI SoC memory architecture and learn about the advantages of SRAM, ReRAM, MRAM, and beyond.The post The Importance of Memory Architecture for AI SoCs appeared first on Chip Design....
Nov 6, 2023
Suffice it to say that everyone and everything in these images was shot in-camera underwater, and that the results truly are haunting....

featured video

Dramatically Improve PPA and Productivity with Generative AI

Sponsored by Cadence Design Systems

Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.

Click here for more information

featured paper

Power and Performance Analysis of FIR Filters and FFTs on Intel Agilex® 7 FPGAs

Sponsored by Intel

Learn about the Future of Intel Programmable Solutions Group at intel.com/leap. The power and performance efficiency of digital signal processing (DSP) workloads play a significant role in the evolution of modern-day technology. Compare benchmarks of finite impulse response (FIR) filters and fast Fourier transform (FFT) designs on Intel Agilex® 7 FPGAs to publicly available results from AMD’s Versal* FPGAs and artificial intelligence engines.

Read more

featured chalk talk

Package Evolution for MOSFETs and Diodes
Sponsored by Mouser Electronics and Vishay
A limiting factor for both MOSFETs and diodes is power dissipation per unit area and your choice of packaging can make a big difference in power dissipation. In this episode of Chalk Talk, Amelia Dalton and Brian Zachrel from Vishay investigate how package evolution has led to new advancements in diodes and MOSFETs including minimizing package resistance, increasing power density, and more! They also explore the benefits of using Vishay’s small and efficient PowerPAK® and eSMP® packages and the migration path you will need to keep in mind when using these solutions in your next design.
Jul 10, 2023
17,783 views