editor's blog
Subscribe Now

Serial Protocol Chameleon

We recently looked at Tektronix’s strategy for their new Veridae acquisition, but we also looked more broadly at their overall focuses, one of which is on serial links. They recently demonstrated a platform for testing such links.

There’s been a tendency for test boxes to be confined to individual protocols or families of protocols; their main point here is the integration of numerous protocols in the one box. Specifically, they list as examples Ethernet, Fibre Channel, Common Public Radio Interface (CPRI), and Serial Front Panel Data Port (FPDP). Or any combination of those.

But they also have a means for users to define their own protocols.

The other thing that tends to create a multiplicity of boxes on the benchtop is the function: pattern generators, for example, are different from analyzers. Their proposal is that a single box can act as protocol analyzer, traffic generator, system stress tester, or bit-error-rate tester – or any combination of those.

But don’t go looking for this just yet on the shelves of your neighborhood protocol analyzer dealer. This was a technology demonstration at ESC Boston. Although, it almost sounds like a product isn’t far behind…

More info in their release… (and hopefully more when released)

Leave a Reply

featured blogs
Jul 25, 2025
Manufacturers cover themselves by saying 'Contents may settle' in fine print on the package, to which I reply, 'Pull the other one'”it's got bells on it!'...

featured paper

Agilex™ 3 vs. Certus-N2 Devices: Head-to-Head Benchmarking on 10 OpenCores Designs

Sponsored by Altera

Explore how Agilex™ 3 FPGAs deliver up to 2.4× higher performance and 30% lower power than comparable low-cost FPGAs in embedded applications. This white paper benchmarks real workloads, highlights key architectural advantages, and shows how Agilex 3 enables efficient AI, vision, and control systems with headroom to scale.

Click to read more

featured chalk talk

Vector Funnel Methodology for Power Analysis from Emulation to RTL to Signoff
Sponsored by Synopsys
The shift left methodology can help lower power throughout the electronic design cycle. In this episode of Chalk Talk, William Ruby from Synopsys and Amelia Dalton explore the biggest energy efficiency design challenges facing engineers today, how Synopsys can help solve a variety of energy efficiency design challenges and how the shift left methodology can enable consistent power efficiency and power reduction.
Jul 29, 2024
262,848 views