industry news
Subscribe Now

Altera Releases Quartus II Software Arria 10 Edition v14.0

San Jose, Calif., August 18, 2014 – Altera Corporation (Nasdaq: ALTR) today released Quartus® II software Arria® 10 edition v14.0, the industry’s most advanced 20 nm FPGA and SoC design environment. Altera’s proven Quartus II software delivers the fastest compile times and enables the highest performance for 20 nm FPGA and SoC designs in the industry. Customers can further accelerate their Arria 10 FPGA and SoC design cycles by using the broad portfolio of 20 nm-optimized IP cores included in this latest software release.

Altera’s 20 nm design tools feature the most advanced algorithms and deliver the highest quality of results in the industry. The Quartus II software Arria 10 edition v14.0 provides on average 2X faster compile times compared to the nearest competitor’s 20 nm design software. This productivity advantage allows customers to shorten design iterations and rapidly close timing on their 20 nm design. The software also enables the highest performance 20 nm designs – providing customers more than a one-speed grade performance advantage over competitive FPGAs.

Included in the latest software release is a full complement of 20 nm-optimized IP cores to enable faster design cycles. The IP portfolio includes standard protocol and memory interfaces, DSP and SoC IP cores. Altera also optimized its popular best-in-class IP cores for Arria 10 FPGAs and SoCs, which include 100G Ethernet, 300G Interlaken, Interlaken Look-Aside and PCI Express Gen3 IP. When implemented in Altera’s Arria 10 FPGAs and SoCs, these best-in-class IP cores deliver the highest performance in the FPGA industry.

A full list of the features and capabilities offered in this software release can be found at http://www.altera.com/b/quartus-ii-arria-10-edition.html

Industry’s Highest Performance 20 nm FPGAs and SoCs
Arria 10 FPGAs and SoCs are the most advanced, highest-performance 20 nm FPGAs available today. The devices integrate several industry-leading features that make Arria 10 FPGAs and SoCs well suited to meet the requirements of high-end, high-performance systems.

  • FPGA Industry’s Only 20 nm ARM-based SoCs – Arria 10 SoCs increase system integration by combining a 1.5 GHz dual-core ARM® Cortex™-A9 MPCore™ hard processor system (HPS) and embedded peripherals with FPGA logic, DSP blocks, high-speed interfaces and memory.
  • Only FPGAs with Hardened IEEE 754 Floating Point DSP – Arria 10 FPGAs and SoCs deliver up to 1.5 TFLOPs of DSP performance to address an expanding range of computationally intensive applications in high-performance computing (HPC), radar, scientific and medical imaging.
  • Highest Serial Bandwidth – Arria 10 FPGAs and SoCs deliver an industry-leading 3.6 Tbps of serial bandwidth with 96 transceiver lanes, the most transceiver lanes and bandwidth in its class.

Pricing and Availability

The Quartus II software Arria 10 edition v14.0 is available now for download at www.altera.com/quartus-arria10. The software is available as a subscription edition and includes a free 30-day trial. The annual software subscription is $2,995 for a node-locked PC license. Engineering samples of Arria 10 FPGAs are shipping today. For additional information about Arria 10 devices, contact your local Altera sales representative or visit www.altera.com/arria10.

About Altera

Altera® programmable solutions enable designers of electronic systems to rapidly and cost effectively innovate, differentiate and win in their markets. Altera offers FPGAs, SoCs, CPLDs, ASICs and complementary technologies, such as power management, to provide high-value solutions to customers worldwide. Visit Altera at www.altera.com.

Leave a Reply

featured blogs
Apr 26, 2024
LEGO ® is the world's most famous toy brand. The experience of playing with these toys has endured over the years because of the innumerable possibilities they allow us: from simple textbook models to wherever our imagination might take us. We have always been driven by ...
Apr 26, 2024
Biological-inspired developments result in LEDs that are 55% brighter, but 55% brighter than what?...
Apr 25, 2024
See how the UCIe protocol creates multi-die chips by connecting chiplets from different vendors and nodes, and learn about the role of IP and specifications.The post Want to Mix and Match Dies in a Single Package? UCIe Can Get You There appeared first on Chip Design....

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

Introduction to the i.MX 93 Applications Processor Family
Robust security, insured product longevity, and low power consumption are critical design considerations of edge computing applications. In this episode of Chalk Talk, Amelia Dalton chats with Srikanth Jagannathan from NXP about the benefits of the i.MX 93 application processor family from NXP can bring to your next edge computing application. They investigate the details of the edgelock secure enclave, the energy flex architecture and arm Cortex-A55 core of this solution, and how they can help you launch your next edge computing design.
Oct 23, 2023
24,437 views