SAN JOSE, CALIF. –– May 8, 2014 –– ProPlus Design Solutions, Inc., the leading technology provider of giga-scale parallel SPICE simulation, SPICE modeling solutions and Design-for-Yield (DFY) applications, today announced immediate availability of NanoSpice™ Giga, a high-capacity, high-performance parallel SPICE simulator for giga-scale circuit simulation for memory applications.
Targeted to emerging giga-scale SPICE simulation needs, NanoSpice Giga is the follow-on product to NanoSpice™, a high-performance parallel SPICE simulator introduced early last year, and shares the same innovative licensing model for parallelization as NanoSpice.
Giga-scale SPICE simulation is a term used to describe simulators that can solve large-scale circuit simulation challenges where FastSPICE cannot meet accuracy requirements and traditional SPICE simulators are limited by capacity.
To meet accuracy needs, NanoSpice Giga remains a pure SPICE simulator by solving the full matrix and analytical device model calculations without approximations. It uses a newly designed database for efficient memory handling and innovative matrix solver technology to handle giga-scale element circuits. Effective model-handling and high-performance parallelization technology enable NanoSpice Giga to deliver competitive performance when compared to FastSPICE simulators. With NanoSpice Giga, users can get reliable simulation results with no need to experiment with complicated partitioning and other FastSPICE options.
NanoSpice and NanoSpice Giga share the same core SPICE engine with ProPlus’ de-facto golden device modeling software BSIMProPlus™, used by all leading foundries, resulting in built-in foundry-validated accuracy and compatibility for all mainstream and leading-edge technologies including 16/14-nanometer (nm) FinFET. The simulators have full SPICE analysis features and support industry-standard inputs and outputs.
NanoSpice Giga was created primarily for large-scale memory circuit simulations, including the characterization of large embedded SRAM blocks, and simulation and verification of memory integrated circuits (ICs) such as SRAM, DRAM and flash memory, typically the domain of FastSPICE simulators. With shrinking technology, supply voltage reductions and the impact of increasing process variations, memory circuit simulation requires better accuracy, increasing limitation of FastSPICE simulators. Memory designers are looking for alternative solutions such as NanoSpice Giga that naturally provide SPICE accuracy without capacity compromises.
Recently, NanoSpice Giga handled a 495-million element post-layout SRAM simulation. It took 11.37 hours to finish the entire simulation on a 24-core computer server consuming 69.1-gigabite (GB) of memory, while a FastSPICE simulator run took 15.3 hours and 173GB of memory to finish the same simulation, and did not meet accuracy requirements. NanoSpice Giga can scale to more than one-billion elements for postlayout simulation of the largest memory designs.
“Memory characterization and verification are challenging, especially when we’re moving to advanced nodes like FinFET,” says Dr. Zhihong Liu, executive chairman and chief executive officer of ProPlus Design Solutions. “NanoSpice Giga beats a FastSPICE simulator’s accuracy and overcomes a SPICE simulator’s capacity limit to provide an accurate, reliable and high-performance solution for large-scale memory simulations.”
In addition to block-level or full-chip memory circuit verifications, NanoSpice Giga is integrated with ProPlus’ DFY platform NanoYield™ to provide a total solution for memory designs. The integrated DFY platform can be used for 4-7+ sigma memory bitcell and peripheral circuit design, based on the industry’s leading high-sigma technology licensed from IBM.
NanoSpice Giga is shipping now. Pricing is available upon request.
ProPlus at DAC
ProPlus will demonstrate NanoSpice Giga and its FinFET-ready DFY products for nano-scale SPICE modeling and giga-scale SPICE simulation at the 51st Design Automation Conference (DAC) in Booth #905. DAC will be held Monday, June 2, through Wednesday, June 4, from 9 a.m. until 6 p.m. at the Moscone Center in San Francisco. To schedule a meeting or demonstration, send email to: dac@proplussolution.com.
Dr. Bruce McGaughy, ProPlus’ chief technology officer and senior vice president of engineering, will participate in a pavilion panel, “Giga-Scale Design Challenges: Billions and Billions of Transistors.” It will be held Monday, June 2, from 11:30 a.m. until 12:15 p.m. on the DAC exhibit floor in the Pavilion (Booth #313).
More information about DAC is available at: www.dac.com.
About ProPlus Design Solutions
ProPlus Design Solutions, Inc. (www.proplussolutions.com) delivers Electronic Design Automation (EDA) solutions with the mission to enhance the link between design and manufacturing. It is the global leader for SPICE modeling solutions and the leading technology provider for unique Design-for-Yield (DFY) products that integrate the key DFY components ––advanced device modeling software, a parallel SPICE simulation circuit simulator and hardware-validated statistical variation analysis tools. Products include: BSIMProPlus™/Model Explorer™, a modeling technology platform for nanometer devices; NoisePro™/9812B/9812D, the golden solution for low-frequency 1/f noise and Random Telegraph Signal (RTS) noise characterization and process monitoring; NanoSpice™, a high-capacity, high-performance parallel SPICE simulator for giga-scale circuit simulation; and NanoYield™/NanoExplorer™, a variation analysis platform for yield versus power, performance and area trade-off of memory, analog and digital circuit designs. ProPlus Design Solutions has R&D centers in the San Jose, Calif. and Beijing and Jinan, China, with sales offices in Tokyo, Japan, Hsinchu, Taiwan, and Shanghai, China. More information about ProPlus Design Solutions can be found at www.proplussolutions.com.
