industry news
Subscribe Now

ASSET ScanWorks high-speed I/O validation tools are first for Intel Atom micro server designs

Richardson, TX (August 15, 2012) ? Designers of micro server circuit boards based on the Intel® Atom? processor now have for the first time a tool capable of non-intrusively validating the signal integrity on high-speed input/output (HSIO) and memory buses. The ScanWorks® platform for embedded instruments from ASSET® InterTech is the first design validation tool for Intel Atom designs that does not rely on placing a physical probe on a bus to monitor its signal integrity.

ASSET (www.asset-intertech.com) is the leading supplier of validation, test and debug tools for embedded instrumentation. 

Over the last eight years, Intel and ASSET have collaborated on validation and test tools which deliver extensive visibility of the signal integrity on high-speed buses in order to overcome the shortcomings of legacy intrusive probe-based test equipment such as oscilloscopes and logic analyzers. Because buses with speeds in excess of 5 gigabits per second (Gbps) become super-sensitive to capacitive coupling effects, the signaling on these buses is distorted when a physical probe is placed on them. To counteract this, Intel developed and is implementing an instrumentation technology that is embedded in its advanced chips. ASSET?s ScanWorks HSIO for Intel Architecture (IA) is the first and only non-intrusive software-based toolkit to take advantage of Intel?s embedded instrumentation technology. 

?The speed of memory and I/O buses on micro server designs is just as critical to the throughput of the system as is the speed of the Intel Atom processor itself,? said Tim Caffee, ASSET?s vice president of design validation and test. ?Thoroughly validating these types of designs requires advanced tools that do not require physical access to the bus. Most of these designs do not provide test pads or points on the buses because they only introduce anomalies into the signaling and degrade its performance. That?s why non-intrusive tools like ScanWorks are becoming a necessity.?

The ScanWorks HSIO validation tools now support all of Intel?s processor platforms, including Intel Core? processors for desktop, mobile and ultrathin laptops, Intel Xeon® processors for servers, embedded and communications, and storage systems, and now Atom processors for micro servers, system-on-a-chip (SoC) and other types of systems. ASSET is a key third party vendor (TPV) to Intel.

?The buses on Intel Atom micro server designs have the same kinds of issues as the high-speed buses have on other Intel platforms,? Caffee said. ?During the last eight years, we?ve developed a close working collaboration with Intel. Now, it?s paying off for Intel Atom designers with a fourth-generation product.?

Pricing and Availability

ScanWorks High-Speed I/O (HSIO) for Intel® Architecture (IA) based on Intel® Atom? is available now. Pricing for a one-year subscription is $10,000. For more information, call 888-694-6250, fax 972-437-2826, e-mail ai-info@asset-intertech.com or visit www.asset-intertech.com

About ASSET InterTech

ASSET InterTech is the leading supplier of tools for embedded instrumentation for design validation, test and debug. The ScanWorks platform provides automation, access and analysis tools in one environment. Users can quickly and easily validate and test chips or circuit boards during every phase of a product’s life, including design, manufacturing/repair and field maintenance. ASSET InterTech is located at 2201 North Central Expressway, Suite 105, Richardson, TX 75080.

Leave a Reply

featured blogs
Apr 26, 2024
LEGO ® is the world's most famous toy brand. The experience of playing with these toys has endured over the years because of the innumerable possibilities they allow us: from simple textbook models to wherever our imagination might take us. We have always been driven by ...
Apr 26, 2024
Biological-inspired developments result in LEDs that are 55% brighter, but 55% brighter than what?...
Apr 25, 2024
See how the UCIe protocol creates multi-die chips by connecting chiplets from different vendors and nodes, and learn about the role of IP and specifications.The post Want to Mix and Match Dies in a Single Package? UCIe Can Get You There appeared first on Chip Design....

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

Addressing the Challenges of Low-Latency, High-Performance Wi-Fi
In this episode of Chalk Talk, Amelia Dalton, Andrew Hart from Infineon, and Andy Ross from Laird Connectivity examine the benefits of Wi-Fi 6 and 6E, why IIoT designs are perfectly suited for Wi-Fi 6 and 6E, and how Wi-Fi 6 and 6E will bring Wi-Fi connectivity to a broad range of new applications.
Nov 17, 2023
21,457 views