fresh bytes
Subscribe Now

$600 Shoelace-tying robot was built on a shoestring budget

With a budget of just $600—a mere pittance compared to what robots like ATLAS cost to develop—students from the University of California’s Davis’ College of Engineering created a machine that’s capable of tying a shoe all by itself.

After mastering the skill when you’re five years old, you probably don’t give much thought to the intricate ballet of fingers and laces that’s performed every time you tie your shoes. But in reality, it’s a complicated process. What makes these engineering student’s machine even more impressive is that it’s powered by just two motors, and relies on a series of gears and moving rods to pick up and move a pair of shoelaces around. Read more at Gizmodo

Leave a Reply

featured blogs
Aug 16, 2018
Usually I don't go to the last day of SEMICON West since not much happens that day. But they have got smart, and two of the most interesting sessions took place in TechXPOT (I think you pronounce that Techspot) on Thursday. In the afternoon was Scaling Every Which Way ab...
Aug 15, 2018
VITA 57.4 FMC+ Standard As an ANSI/VITA member, Samtec supports the release of the new ANSI/VITA 57.4-2018 FPGA Mezzanine Card Plus Standard. VITA 57.4, also referred to as FMC+, expands upon the I/O capabilities defined in ANSI/VITA 57.1 FMC by adding two new connectors that...
Aug 15, 2018
The world recognizes the American healthcare system for its innovation in precision medicine, surgical techniques, medical devices, and drug development. But they'€™ve been slow to adopt 21st century t...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...