fish fry
Subscribe Now

Inching Along

Sometimes it feels like we’re just inching along toward innovation. Sometimes it feels like we’re flying by the seat of our pants toward the future without a seatbelt in sight. This week we’re talking about Intel’s long-range plans for a 5nm process node, why ESL should be playing a big role in your next low power design, and even why the cool kids aren’t using discrete components for power supplies anymore.

Also this week, I give away a copy of the book “Mixed-Signal Methodology Guide” courtesy of Cadence Design Systems. 

Listen to this episode
Download this episode (right click and save)

Fish Fry Links – September 21, 2012

More Information about The Embedded Vision Summit at Design East 2012

More Information about The Intel Developer Forum

More Information about Docea Power

More information about Cadence’s new book “Mixed-Signal Methodology Guide”

Leave a Reply

featured blogs
Aug 19, 2018
Consumer demand for advanced driver assistance and infotainment features are on the rise, opening up a new market for advanced Automotive systems. Automotive Ethernet allows to support more complex computing needs with the use of an Ethernet-based network for connections betw...
Aug 18, 2018
Once upon a time, the Santa Clara Valley was called the Valley of Heart'€™s Delight; the main industry was growing prunes; and there were orchards filled with apricot and cherry trees all over the place. Then in 1955, a future Nobel Prize winner named William Shockley moved...
Aug 17, 2018
Samtec’s growing portfolio of high-performance Silicon-to-Silicon'„¢ Applications Solutions answer the design challenges of routing 56 Gbps signals through a system. However, finding the ideal solution in a single-click probably is an obstacle. Samtec last updated the...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...