chalk talk
Subscribe Now

Debug and Verify FPGA Algorithms with MATLAB and Simulink

 

Today’s FPGA designs require industrial-strength functional verification. The ad-hoc methods that worked with older, smaller FPGAs just don’t cut it anymore. In this episode of Chalk Talk, Amelia Dalton chats with Eric Cigan of MathWorks about ASIC-strength functional verification with model-based design.

Click here for more information about how to verify VHDL and Verilog using HDL simulators and FPGA-in-the-loop test benches

Leave a Reply

featured blogs
Jul 16, 2018
This week it is CDNLive Japan on Friday July 20th. I will be there so obviously this will be my latest trip to Japan...but we will start by looking at my first trip to Japan. The first trip I made to Japan was in 1983. This was very early. If you have been in semiconductors o...
Jul 12, 2018
A single failure of a machine due to heat can bring down an entire assembly line to halt. At the printed circuit board level, we designers need to provide the most robust solutions to keep the wheels...
Jun 29, 2018
Once you'€™ve made the correct decision to add Speedcore eFPGA IP to your ASIC or SoC design, the next question you'€™ll need to answer is how large to make the eFPGA. That'€™s a multi-dimensional question because Speedcore eFPGAs contain many types of blocks including:...