editor's blog
Subscribe Now

Room-Temp Covalent Wafer Bonding

MEMS elements are delicate. They sit there in their little cavities, expecting to operate in some sort of controlled environment – perhaps a particular gas or pressure (or lack of it). And if they’re collocated with CMOS circuitry, then they need to be protected from any further processing steps. In other words, they need to be sealed off from the rest of the world. And wafer bonding is a common way to do that: bring another wafer (perhaps with etched features) face-to-face with the working wafer and get them to bond.

Covalent molecular bonds are the strongest; if you bring two silicon wafers together, for example, the ideal is to have the silicon atoms at the surface of each wafer bond covalently with their counterparts on the other wafer so that the whole thing starts to look like a continuous crystal. That’s the ideal.

Doing this isn’t trivial, of course, since the surfaces are likely to have imperfections and contaminants. So surface preparation has been an important part of the wafer bonding process. It has also involved intermediaries like water that establish a preliminary bond; an anneal then precipitates the reactions that result in the appropriate covalent bonds and out-diffusion of any extraneous elements.

Initially, high temperatures were required for the annealing. But, of course, anything over 450 °C won’t sit well with any CMOS that might be in place, so various surface preparation techniques have been devised to get the anneal temps down below that threshold.

But even these temperatures can be an issue for bonding unlike materials, or for wafers that have unlike materials in the stack, where stresses can result from differing rates of thermal expansion during the anneal process.

EVG has recently announced a new way of preparing the surface so that covalent bonding occurs immediately, at room temperature. To be clear, they have announced that they have this new process; they haven’t announced what it is; they’re still being coy on that. This eliminates the annealing step completely, and therefore the thermal expansion issue as well.

Equipment using this new technique should ship sometime this year. You can find out more in their release.

Leave a Reply

featured blogs
Apr 25, 2024
Structures in Allegro X layout editors let you create reusable building blocks for your PCBs, saving you time and ensuring consistency. What are Structures? Structures are pre-defined groups of design objects, such as vias, connecting lines (clines), and shapes. You can combi...
Apr 25, 2024
See how the UCIe protocol creates multi-die chips by connecting chiplets from different vendors and nodes, and learn about the role of IP and specifications.The post Want to Mix and Match Dies in a Single Package? UCIe Can Get You There appeared first on Chip Design....
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

Unlock the Productivity and Efficiency of a Connected Plant
In this episode of Chalk Talk, Amelia Dalton and Patrick Casey from Schneider Electric explore the multitude of benefits that mobility brings to industrial applications. They investigate how Schneider Electric’s Harmony Hub can simplify monitoring and testing, increase operational efficiency and connectivity openness in industrial plants, and how NFC technology can bring new innovation possibilities to IIoT applications.
Apr 23, 2024
446 views