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Living in the Product Development

Fiscal Focus

The recent downturn in the semiconductor industry, unprecedented in its magnitude and duration, has forced application specific standard product (ASSP) vendors to improve the fiscal efficiency of their product development processes and capabilities, with the intent of maximizing return-on-investment (ROI). Improving development capability and efficiency will lower non-recurring costs, and will also lower the cost of goods sold (COGS), resulting in improved profitability. Successful ASSP companies understand the fiscal benefit of strong design capability and actively seek opportunities for improvement.

< … Read More → "Living in the Product Development"

Customer-Specific FPGAs


The risks associated with ASIC solutions increase in magnitude with the move to smaller process geometries. This coupled with the increase in design complexity is compelling companies to look for viable technology options that offer low unit and total costs, high-level of system integration, wide selection of IP, design flexibility with faster time to market, and no/minimal incremental design or design tool investment. Such alternatives must also avoid the pitfalls of ASICs that include high NRE and re-spin expenses, slow turn around times, and complexity of the design environment and ecosystem, and hidden … Read More → "Customer-Specific FPGAs"

Cost-Reduction Quagmire

Your design is working perfectly – on your development board.

Unfortunately, your company is probably not planning to ship FPGA development boards as part of their product. You’ll have to come up with something a little more practical and cost effective if you’re going to win “employee of the decade” when your skunk-works design ships one million units.

There is general consensus, even among ASIC suppliers, that FPGAs are the highest productivity platform for getting your design debugged and running in actual hardware. If you have an idea, and you want a hardware … Read More → "Cost-Reduction Quagmire"

Benchmarking Battlefield

In our previous article “Terminology Tango 101” we poked fun at the myriad metrics given by programmable logic companies in their publications and data sheets. While it’s fun to make fun of the confusion induced by this dizzying data, it is also interesting and useful to dig past the difficulties of agreeing on units and dimensions and to take a look at the actual processes that are used to test our tools and evaluate our architectures. While there is a good deal of obfuscation built into the … Read More → "Benchmarking Battlefield"

Overview of Memory Types and DDR Interface Design Implementation

Memory Overview

Over the past several years the electronics market and, more specifically, the memory market has undergone significant change. Prior to the electronics industry downturn in 2000, electronic system designers were less concerned with the cost of the components going into their next design, and more concerned with the raw, maximum performance they could achieve.

Today, increasing competition and decreasing profit margins have forced system designers to reduce next generation product cost while maintaining, or even increasing, system performance. One industry segment that has experienced substantial growth as a result of this transition … Read More → "Overview of Memory Types and DDR Interface Design Implementation"

High DRAMa

A decade ago, memory was not mentioned in the same breath as programmable logic. Each component type had its own role in system design, and different design team members were typically involved with their selection and use. Once FPGAs became serious system components, they began to be paired with memory in switching and network applications. During that period, however, the cost of the FPGAs (sometimes thousands of dollars per device) usually dwarfed the RAM budget. Memory was selected for its speed, and interfacing was a simple matter of putting out an address and latching in some data.

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Package Deal

Choosing an FPGA package is both simple and fun.

We have flat-pack, via-stack, timing sometimes outa’ whack; BGA, pin-array, tin-whisker sneak attack, lead-free, QFP, 12-layer PCB; cavity-up, cavity-down, ceramic, plastic, heat-sink ground; flip-chip, classic DIP, moisture-sensitive micro-chip… OK, wait. Let’s break this down.

Package selection is one of the most important and least understood aspects of part selection for most FPGA designers. While the digitally inclined among us are savvy to the subtleties of speed-grade selection and cognizant of the complexities of LUT-counting, we tend to glaze over at mere mention … Read More → "Package Deal"

Does Single-pass Physical Synthesis Work for FPGAs?

As mask prices and NRE costs rise to exorbitant levels, the ASIC route becomes increasingly unrealistic for many applications, especially in low- to medium-volume production quantities. Design starts using ASICs have plummeted from a high of over 11,000 in 1997 to below 4,000 in 2003 (Source: Gartner Dataquest). With the advent of innovative FPGA architectures incorporating embedded processors, memory blocks and DSP functions, many designers who depended on ASIC methodologies are turning to FPGAs for new generations of complex designs. The problem is that, increasingly, these designers are the same person, i.e., one day they are designing an ASIC and the next … Read More → "Does Single-pass Physical Synthesis Work for FPGAs?"

Engineers Speak Out

A few weeks ago, in our “What’s your Persona?” feature article, we discussed the fact that Xilinx is creating new divisions for DSP and embedded processing. We speculated that the idea of focusing on specific categories of new potential FPGA customers, creating groups inside the FPGA company that understand the design challenges and speak the technical jargon of each emerging subculture, would be a compelling strategy.

We then decided to test that theory by asking you to drop … Read More → "Engineers Speak Out"

Energy Efficient Application Design using FPGAs

Traditionally, FPGAs are not considered suitable for low-power application design because of higher quiescent power, significant energy dissipation during start-up, and higher dynamic power due to longer interconnects and overheads for reconfigurability. However, with advances in FPGA manufacturing technologies and growing demand for feature-rich mobile applications in both civilian and military communities FPGAs are being considered an attractive device for applications deployed in power-constrained environments. Some of the reasons for considering FPGA for energy efficient application design are:

In general, FPGAs are denser, use lower supply voltage, and provide more computation per Watt than … Read More → "Energy Efficient Application Design using FPGAs"

featured blogs
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Look around, look around at how lucky we are to be alive right now'€¦ '€”Lin-Manuel Miranda, Hamilton Every once in a while, I write a post like this one, to highlight some of the amazing things that are happening in the world of electronics and technology. Today I culled...
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Oct 16, 2018
  IC Insights has just published the September Update to The 2018 McClean Report, and one figure (reproduced below) puts yet another nail into the coffin for poor old Moore'€™s Law. Now please take care. There'€™s a vertical line between the 200mm wafers on the left ...
Oct 12, 2018
At the end of the day, your products are only as good as their in-the-field performance. It doesn'€™t matter how well they performed in a controlled environment....