Intel announced last week that they are acquiring structured ASIC company eASIC into their Programmable Systems Group (PSG). If you haven’t been following along in your major merger primer, Intel PSG was formerly known as Altera – one of the two major players in the FPGA market. Altera has played second fiddle to Xilinx in the Duopoly Symphony for the past twenty seasons or so. This acquisition is the most recent strategic move in the longstanding rivalry between the two companies, and it raises the level of intrigue substantially in the competitive arena.

So, who is eASIC, what is a “structured ASIC”, and why would Intel need to buy a small semiconductor company whose chips are manufactured by rival TSMC? For those of us who are old enough to remember 2003 (coincidentally, the year this publication was founded), structured ASIC made a big splash – arriving on the scene as a high-value “in between” alternative that filled the huge gap between FPGAs and standard-cell-based ASICs. FPGAs were big, slow, expensive, power hungry, and (on the upside) offered fast time-to-market, zero NRE, and in-system reprogrammability (to fix those pesky errors that resulted from less-than-ASIC verification practices.) ASICs had huge NRE costs and very long development times, but they clobbered FPGAs on unit cost, power consumption, and performance. This is still all pretty much true today, by the way.

Structured ASIC borrowed from the 1980s “gate array” playbook (for those of us even older). Gate arrays, which predated standard-cell ASICs, were pre-designed and pre-manufactured chips consisting (mainly) of an array of unconnected logic gates that could be configured after the fact – by adding a couple of metal layers – to implement a custom logic function. Gate arrays had much lower NRE than full custom chips because only a couple metal layers worth of masks were required to create a custom device. The downside of gate arrays was that you had to choose a base array that was bigger than your design required (and the unused gates were wasted) and the implementation of any given function was bound to be suboptimal because the arrangement of gates in the base array was fixed and not optimized for the data flow of any particular function. To pick an important example, a multiplier implemented in gate array logic would be substantially slower and less efficient than one implemented as a custom cell.

Fast forward a bit and we get, of course, “Field Programmable Gate Arrays” (FPGAs), which took the concept of gate arrays one step further, eliminating the customization steps altogether and creating a truly desktop-customizable device by replacing the NAND gates from typical gate arrays with look-up-table (LUT) cells whose logic functions could be dynamically programmed, and swapping those customization metal layers with a switchbox-like matrix of SRAM cells – allowing the routing between LUTs to be dynamically configured in the field. So, gate arrays were in some sense the precursors to FPGAs and also the basis for structured ASICs some twenty years later.

The heyday of structured ASIC was short-lived, however. Companies offering structured ASIC solutions were unable to generate enough business to deliver the economy of scale from their base devices that would make them cost-competitive with ASICs on a per-unit basis, and the NRE turned out to be higher than expected, making their value proposition dicey. There is always a challenge, when offering an “in between” solution, that the gap between the two alternatives will close, leaving the “in between” product with nowhere to go, or that the value proposition for the “in between” solution is too close to one alternative or the other and diminishes to zero. Some combination of these effects was most likely responsible for the demise of structured ASIC as a mainstream technology.

Structured ASIC didn’t die entirely, however. eASIC, for example, came up with some novel tricks that reduced the customization to a single via layer – thus improving the NRE and overall cost part of the equation – and they were clever enough with their base array design to fit a large and important swath of applications well. But one of the biggest holdouts for structured ASIC technology turned out to be… Altera.

Ah, we’ve come full circle.

Altera launched a structured ASIC product called “Hard Copy” back in the mid-2000s. Hard Copy allowed a customer who had a working FPGA implementation of their design to somewhat-magically turn their FPGA into an ASIC, resulting in the usual benefits – lower power, higher performance, smaller die, and lower unit cost. Altera accomplished this by building structured ASIC base arrays that mirrored the features of their FPGAs, but using hardened versions of the LUTs and metal layers instead of the programmable logic SRAM interconnect. In doing so, Altera hit on what may be the “killer app” for structured ASIC: FPGA conversion. At the same time, they created a completely new flow for ASIC design – one-to-one prototyping and early production with FPGA, followed by a low-cost, low-risk, fast-turnaround, repeatable process for reducing BOM cost and improving performance and power consumption.

This immediately got the attention of arch rival Xilinx, who quickly put together a “we have one too” offering called EasyPath. EasyPath was a brilliant piece of marketing on Xilinx’s part. It was not a structured ASIC – or any kind of ASIC for that matter. Xilinx would simply sell you the same FPGAs you were already using for a much lower cost. The catch? Those FPGAs were pre-tested using your design. They were not given the usual degree of testing required for “general purpose” FPGAs. If your design didn’t happen to use a particular multiplier, for example, that multiplier would most likely not be tested in the EasyPath parts you were shipped. By cutting testing costs (and cutting margins a bit as well, we presume) Xilinx was able to offer EasyPath to counter Altera’s HardCopy.

EasyPath didn’t bring some of the benefits of HardCopy, of course. The power consumption and performance were identical to the original FPGA because these parts were, in fact, the original FPGA. On the upside, that meant there was no NRE required, and no effort whatsoever converting your design from FPGA to EasyPath FPGA. There was a fierce marketing battle between the two companies, resulting in (from what we could see) very little commercial market traction.

It appears that both Altera and Xilinx quietly either dropped or severely de-emphasized their HardCopy and EasyPath offerings over time. Other new-and-shiny more interesting marketing battlefields emerged that allowed the two rivals to continue their oneuppances, and the FPGA companies’ own entries into structured ASIC faded into the sunset.

eASIC, however, persisted. Their particular flavor of structured ASIC got enough design wins to sustain a business, and the company continued upgrading their offering to newer process nodes and addressing new application domains. The company’s nextreme3 and nextreme3s families are built on TSMC 28nm technology and pack up to 52 million ASIC-equivalent gates, 124 Mb of true dual port memory, and 28 Gbps and 16.3 Gbps high speed transceivers. That’s a pretty good approximation of the capabilities of a lot of modern high-end FPGAs. And, eASIC has made a good business picking up the slack from the demise of HardCopy and EasyPath by helping customers convert FPGA designs to structured ASIC replacements.

eASIC has another trick up their sleeve as well – their eASICopy offering provides “a seamless and low risk migration path from eASIC Nextreme-2, eASIC Nextreme-3 or eASIC Nextreme-3S to a lower-unit-cost, cell-based ASIC. In Altera parlance, they are offering “Harder-Copy” with presumably zero compromise for low NRE and fast turnaround. That gives a 3-stage cost-reduction path – FPGA for prototyping and early production, eASIC structured ASIC for volume production once the design settles down, and eASICopy for a full-blown ASIC solution. As far as mitigating risk and easing into the cost, power, and performance benefits of an ASIC – it’s a compelling story.

So now, eASIC becomes part of Intel PSG (formerly Altera). What are the implications of that? First, there are a number of very active application domains right now that could be well served by structured ASIC technology – particularly with a migration path from FPGA. Neural network inferencing (as we discussed recently) is a great application for FPGAs, as the fixed-point parallelizing prowess of programmable logic really shines when it comes to evaluating inputs against a trained CNN and getting results with minimal latency and power. But, if you have an FPGA version of NN inferencing working and want to further reduce cost and power while further increasing performance, a structured ASIC (and possibly full-ASIC) migration path could be a major advantage.

Competitively, this does several things for Intel PSG versus Xilinx. First, it would seem to bring back HardCopy with a vengeance. Xilinx could try to resurrect EasyPath in response again, but that ship likely has sailed. The big story with eASIC is not just unit cost reduction – it’s “up to 80% power reduction” and substantial performance improvements as well. EasyPath never did anything to reduce power or improve performance. It simply reduced cost.

Second, eASIC currently offers migration of both Intel/Altera FPGAs and Xilinx FPGAs. This gives Intel a way to scoop up Xilinx FPGA sockets with a structured ASIC conversion play. Xilinx could score wins for FPGAs during prototyping, only to have the big-bucks volume go to Intel later on.

Regarding the semiconductor technology base, eASIC is already using TSMC as their foundry, so that should put them on at least a level playing field with Xilinx in terms of process technology. If Intel process technology ends up being more attractive, eASIC would have the option for that as well. That means that Xilinx would not be able to make a viable case for TSMC being their advantage, as TSMC is building parts for both companies. And, conversion to structured ASIC or full ASIC will absolutely bring more performance, cost, and power advantages than a process lead in FPGA technology – even if the ASIC or structured ASIC is on a less-advanced process node.