feature article
Subscribe to EE Journal Daily Newsletter

DynamIQ Tension

ARM’s DynamIQ Interface is Nice, Not Spectacular

“As a rule, a beautiful woman is a terrible disappointment.” – Carl Jung

You want the short version? Some future ARM processors will support 8-CPU clusters.

You want the longer version? “This redefines multicore. Designed from the ground up. Massive system performance uplift. 10x faster. 50x faster. Architecture for total computing. An industry inflection point. Accelerates AI adoption. Safer autonomous systems. For all markets and all devices. Nearly ‘unlimited’ design spectrum. Redefining the future of computing.” And more.

Is it just me, or is the hyperbole getting a bit thick in here?

I swear, every word of that is verbatim from the company PowerPoint deck or press release. You’d think they’d just discovered time travel. I can’t remember the last time I heard such a breathless over-the-top description of a bus-interface upgrade.

Yup, that’s what ARM’s new DynamIQ architecture appears to be: an upgrade to AMBA that allows you to join up to eight ARM cores instead of just two. Try to contain your excitement.

It’s tough, I know. I’ve talked to a lot of ARM people, from the CEO on down, about a lot of different new products, but I’ve rarely heard the company get so fired up. This one sounded like a big deal. Yuuuge. One news site posted 27 different tweets about DynamIQ in one day. Twenty-seven.

Is this a good time to point out that MIPS processors can already combine eight CPU cores?

You know those movies that have great trailers but then turn out to be meh? They’re actually okay movies… they just suffer from over-inflated expectations. If it hadn’t been for all the hype, you probably would’ve liked it just fine, but instead you can’t help feeling a bit disappointed and shortchanged. Welcome to my 90 minutes of DynamIQ.

To quote the company: “DynamIQ is probably the biggest micro-architectural shift since ARM announced 64-bit ARMv8-A in 2011.” Probably true, but that’s damning with faint praise. ARM’s first 64-bit processor was a big deal, and the company has done a fine job of rolling out new versions in the six intervening years. DynamIQ doesn’t measure up to that milestone. It’s only a big deal by default; it’s significant only in comparison to normal CPU announcements.

DynamIQ is ARM’s name for an upgraded – sorry, “redesigned from the ground up” – internal bus architecture that allows you to cluster up to eight ARM cores. It’s not backward compatible with any existing ARM processor. DynamIQ will work only with future Cortex-A CPU cores that haven’t been announced yet. So for now, you’re still limited to the two-core big.little combination that designers have been using profitably for a few years.

While they were at it, DynamIQ’s designers also added some other nice features to the bus. You’ll eventually be able to control voltage, sleep modes, and clock speeds individually for each of the eight cores in the cluster. Currently, big.little pairs are powered and clocked together. There’s also some “restructuring of cache systems,” which seems sensible. Eight-core clusters use caches differently than dual-core systems do, so some changes were inevitable.

Is this another good time to mention that MIPS can already do those things, too?

DynamIQ apparently has lower latency than the current interface, probably enabled by a higher bus frequency. I say “apparently,” because ARM didn’t exactly explain it that way. Instead, they used phrases like “faster responsiveness” and “quicker safety-critical decision-making” and “faster task migration.” Sounds like improved latency to me; what do you think?

To quote further: “New dedicated instructions for AI [artificial intelligence] and ML [machine learning] will deliver a 50x boost in AI performance over the next 3–5 years” and “…up to 10x quicker response to accelerators.”

Yet when asked directly how these impressive – indeed, spectacular – improvements might come about, ARM said that “outside companies” and “third parties” and “innovative startups” are doing “really interesting things” with hardware and software. In other words, those speedups are coming from somebody else, at some time, somehow, probably.

I’m sure the new Cortex-A processors due later this year will be wonderful. Just like today’s Cortex-A processors, but better. And you’ll be able to glue eight of them together, not just two. Some tweaks to the instruction set should brighten programmers’ days. But an “inflection point” that “redefines multicore?” Nah.

Years ago, my neighbor was planning to take his kids to the park, then to the new Disney movie playing at the local theater. Somehow, the kids misunderstood and thought they were going to Disneyland. They were excited. They told their friends. They packed clothes. They imagined their visit with Mickey. When the day finally arrived and the reality of the situation dawned, the kids were in tears, mortally disappointed. What could have been a very nice outing turned into childhood trauma. The kids were inconsolable and the parents felt terrible, as well as terribly confused. What did we do wrong?

Managing expectations is a big part of marketing. (And engineering, come to think of it.) I expect that ARM’s new processors with DynamIQ support will be just fine. Sensible designers will deploy them in many interesting ways, in all sorts of products, in many different industries. That should be enough. Don’t try to make it into a trip to Disneyland.

1 thought on “DynamIQ Tension”

  1. Pingback: good seedbox

Leave a Reply

featured blogs
Aug 18, 2017
After leaving the title of yesterday's post in German, the obvious place to go for the next stop on the summer of computer museums is Germany. If you ask people which was the first digital computer, the answer tends to vary with the respondent's nationality. Do comp...
Aug 18, 2017
Bourbon lovers appreciate their favorite spirits in many forms.  Neat. On the Rocks. A favorite mixed drink. An emerging trend in bourbon drinking comes from an unlikely place: Infinite Harvest – an indoor hydroponic vertical farm. Infinite Harvest produces ...
Aug 09, 2017
Recall for a moment a scene—you’ve probably witnessed something like it at trade shows or on video dozens of times. A robot arm moves purposefully from its rest position. It swoops down on an object—a sphere, say—plucks it up, holds it aloft, replaces it, ...
Aug 03, 2017
Speedcore eFPGAs are embeddable IP that include look-up tables, memories, and DSP building blocks, allowing designers to add a programmable logic fabric to their SoC. The Speedcore IP can be configured to any size as dictated by the end application. The SoC supplier defines t...