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FPGAs Race for the Bottom

Intel, Microsemi Debut New Families

There is an awful lot of chest beating in the FPGA world. Xilinx and Intel (Altera) have always taken great biennial pride and few prisoners when it comes to building and bragging about the biggest, baddest, fastest, farthest-out slabs of silicon that a few billion dollars worth of semiconductor fab can crank out. Getting to market before the other guy with a high-end Virtex or Stratix family, released on the latest and greatest FinFET-having, low- or high- or we-don’t-care-anymore-K dielectric, tiniest-geometry, most-exotic process has always been the source of utmost pride for the pair of programmable logic provocateurs.

Then, things usually get quiet for awhile.

Months pass, and then… ever so slowly, the companies’ bleary-eyed marketing machines stagger out of bed, still reciting TeraFLOPS tallies and double-digit Gbps claims after their deep night-before-the-morning-after technology-hype comas, only to realize, “Oh, yeah – we should do something about the FPGAs almost everybody actually USES as well.” 

And then we start talking about “cost-optimized portfolios.”

So then, hype fans – pop a couple of metaphoric Alka-Seltzers, shave off some of that multi-million-LUT stubble, and let’s talk about some FPGAs you’re way more likely to design into your next project. For a full “scenes from the previous episode” experience, we should start off by mentioning that Xilinx announced their new cost-optimized portfolio last September. It included a reborn Spartan line, an update to the now-one-step-up-the-chain Artix, and a new lower-cost member of the processor-having Zynq family. Those announcements laid down a baseline for us to use to evaluate two new and interesting reveals this week from Intel (Altera) and… wait, who? Microsemi? Yep. Microsemi. 

Starting with the expected, Intel is rolling out their Cyclone 10 line with some very impressive details. If you thought you knew the definition of “cost-optimized FPGA,” be prepared to have your notions challenged. Not that many years ago, FPGAs like Cyclone 10 would have been serious contenders as high-end devices, with 4- or 5-digit price tags to match. Intel now has 3 tiers to its “Generation 10” FPGA offering – Stratix 10, Arria 10, and now Cyclone 10. Stratix 10 is fabricated on Intel’s 14nm Tri-Gate (Intel’s name for FinFET) process, and Arria 10 and the new Cyclone 10 are both fabricated on TSMC 20nm planar process. Yep. It’s true. TSMC is building chips for Intel.

Cyclone 10 comes in two flavors – Cyclone 10 GX and Cyclone 10 LP – the main difference being that the GX family packs from four to twelve 10.3 Gbps SerDes transceivers and one or two hard 933 MHz DDR3/L controllers. The GX family has four members, ranging from 85 to 220K LUTs. The LP family has 8 members, from 6K to 120K LUTs. Intel says the new family has “up to” double the speed and “up to .5x power improvement over the Cyclone V family” (a claim which, after a bit of creative parsing, we believe is supposed to mean that, best case, you may drop your power consumption by 50% compared with Cyclone V on the same design at the same clock speed). 

On the performance front, Intel is claiming 300MHz core performance for the Cyclone 10 logic fabric, and they are including up to 384 DSP blocks with 18×19 multipliers and hardened floating point. Memory resources include up to 588 memory blocks with up to 11,760 Kbits of storage, plus up to 1,800 Kbits distributed RAM. Obviously, not the kinds of features that make us think “low-cost” FPGA family. But Intel claims that the cost is about half that of Cyclone V devices of the same density. 

Intel claims that the target markets for the new Cyclone 10 family are Automotive, Industrial, and Embedded Vision. All three of these share characteristics like rapid growth, cost sensitivity, power sensitivity, and appetite for enormous amounts of alternative computing power, which all those DSP blocks bring on in spades. Speaking of computing power, Intel is not announcing an “SoC” version of Cyclone 10, so those who want some ARM cores sprinkled in with their FPGA fabric will need to move up a level or two to Arria 10 or Stratix 10 SoCs.

Before we dive more deeply into the analysis of Cyclone 10, let’s bring in an even more surprising new offering to consider – the new Microsemi PolarFire FPGAs. Microsemi, (particularly the part of Microsemi that was formerly Actel) has been in the FPGA business for a very long time. Microsemi’s FPGAs have generally been targeted at the high-reliability military/aerospace market, and they have been considered “niche” devices because of their modest size, superior performance, and feature set. PolarFire is different. With PolarFire, Microsemi is jumping directly into the cost-optimized low-to-midrange FPGA arena, going head-to-head with Xilinx and Intel.

Microsemi says that PolarFire is positioned for access networks, wireless infrastructure, defense, and industry 4.0 markets, and it has a feature set that lines up favorably with competitive offerings in all those areas, including a few compelling differentiators. Beginning with the different, PolarFire is a non-volatile, flash-based FPGA. That brings some nice advantages in the low-cost market, including removing the need for external configuration circuitry, improving security, reducing startup time, improving low-power standby mode, and reducing power consumption.

With 4 devices ranging from 109K to 481K LUTs, PolarFire defines a new “top” of Microsemi’s density range (the company has lower density families, including IGLOO2 and SmartFusion2, that cover the 6K-150K LUT range). PolarFire packs some substantial SerDes as well, with up to 24 12.7 Gbps transceivers. On the DSP front, PolarFire brings the heat with from 336 to 1,480 hardened 18×18 MAC blocks, and embedded memory weighs in at 7.6 to 33 Mbits. Each device also includes 2 hardened PCIe Gen2 endpoints.

Competitively, these specs put PolarFire straddling Xilinx’s Artix-7 and Kintex-7 families, and, extending into the territory of the new Kintex, UltraScale. Against Intel’s offerings, PolarFire aligns from the middle of the new Cyclone 10 GX up well into the Arria 10 family. PolarFire’s bounty of resources – SerDes, DSPs, memory and overall LUT count – put it squarely in the race for a wide range of sockets, giving its unique flash-related differentiators a chance to shine. 

What specifically are those differentiators? PolarFire inherits some nice attributes from its Microsemi mil/aero heritage. Flash-based FPGAs are inherently more resistant to single-event upsets (SEUs) than conventional SRAM-based FPGAs. Flash-based FPGAs also enjoy significantly lower leakage current, and therefore much lower standby power, than conventional devices. At startup time, there is no inrush configuration current, which is often the peak current demand that drives power supplies for SRAM-based devices. On top of these benefits, the company has built in a hardened crypto processor as well as SGMII (Serial Gigabit Media Independent Interface) for Ethernet. All in all, a compelling set of reasons to take a look at Microsemi’s new kid.

With both of these new offerings hitting the market at once (both companies say they will be shipping silicon well before the end of the year, with some as early as Q2), the choices for cost-optimized FPGA design just got a whole lot more complicated. There is truly an embarrassment of opportunity out there, with crazy numbers of options in the 100K-300K LUT range, including many with rich sets of SerDes, DSP, Memory, and other hardened features, and each with at least some clear differentiators (such as Intel’s hardened floating point and Microsemi’s flash-based non-volatility). 

It is, apparently, a great time to be designing with FPGAs.

 

 

9 thoughts on “FPGAs Race for the Bottom”

  1. Talking about Cyclone 10, I think you should really seperated between GX and LP.

    While GX appears to be a powerful new 20nm family (I am curious about pricing, as the “smallest” part is already quite big), the LP appears to be only a relaunch of Cyclone IV/III (!). I only find it funny, that the claim a 50% power reduction. I could imagine, they claimed about the same from Cyclone IV to Cyclone V 😉

    Don’t get me wrong, I think Cyclone III (and it’s IV die-shrink) was a fantastic family (I would not necessarily say this about V), but it is a bit old-fashined now, and selling this as “new” is a bit hmmm…

    What I am missing for the GX is an SoC version. Maybe there is something in the pipeline? (My last FAE visit is a while back, so I am really not up to date…) Additionally I hope that the GX is not too power hungry…

    Regards,

    Thomas

  2. Hi Thomas,

    Very astute of you to point out that the Cyclone 10LP looks to be a relabeled Cyclone III. Very unlikely it is a new design at 20nm because the core voltage is 1.2v and the packages are exactly the same.

    As far as the Cyclone 10GX, this does not appear to be a new family either. 🙁 It looks to me like they are re-labeling the smaller Arria 10 device. If you look at the transceiver power of both the 10GX and the Arria 10, the power consumption is the same! Bottom line is do not expect Cyclone 10GX to be lower power than Arria 10. If you want a real low power, completely optimized device for mid-range densities the choice is Microsemi PolarFire.

  3. Hi Ted,

    true, now that you say it, it is obvious 😉 Just software limited relaunches of Arria 10… Maybe they did at least a new smaller die for the smaller parts. Would help with power consumption. But I doubt it…

    Hmm, at least it would be nice to get Arria 10 performance for Cyclone pricing. However, they are just a bit too power hungry for most of our applications…

    It’s many years ago since I last worked with Microsemi, but at that time both the tools and the speed of the chip were not very impressive. But maybe things have changed?

    Regards,

    Thomas

  4. I used to use Actel/Microsemi devices. Their Libero IDE software was a nightmare to use. They created Libero SoC which isn’t much better. Now they have Libero SoC PolarFire? Come on guys, get your tools sorted out. Doesn’t matter how good your chips are if your tools are in the dark ages.

    Also, they still don’t fully support Linux. Glad we stopped using Microsemi chips.

  5. We have Linux available if you would like to give our tools another try. Not sure why you did not see that we have Linux. Libero has had numerous improvements, in particular over the last 18 months. In the area of debug tools, our software is head and shoulders better than anyone else. This tool is called SmartDebug. Would love to show you a compelling demonstration.

  6. Ted,

    I did see how you guys don’t fully support Linux. Just go to your site and look at the “Device Support” page for each Libero product (IDE, SoC and SoC PolarFire):
    Firmware Catalog: No Linux support
    SoftConsole: No Linux support
    FlashPro (Libero IDE): No Linux support

    Also:
    “Programming and SmartDebug are not supported in this release and will be added in a service pack mid-March.”
    Wow, releasing chips without full software support…

    And:
    “Programming is not supported on any Virtual Machine (VM)”
    What’s with that limitation?

    Having 3 separate software suites would also be a pain to deal with if you have multiple products that don’t use the same FPGA family.

    You can save your “compelling demonstration” for people who haven’t already used your tools.

  7. CyrilJ,

    You’re links are broken.

    Also, Microsemi’s THREE separate software suites are INCONSISTENT with Linux support.
    – FlashPro for Libero IDE does not support Linux. Microsemi’s site and documentation is all over the place with FlashPro hardware and FlashPro/FlashPro Express software.
    – Firmware Catalog has 0 Linux support.
    – I guess despite their incorrect support matrix, SoftConsole does support Linux. I stand corrected. Although, the latest 5.0 version does not support Windows this time… I can’t stop laughing.

    Seems that I was a victim of their website not being consistent. Their device-support matrices don’t reflect what’s actually supported/not supported:
    https://www.microsemi.com/products/fpga-soc/design-resources/design-software/libero-ide#device-support
    https://www.microsemi.com/products/fpga-soc/design-resources/design-software/libero-soc#device-support
    https://www.microsemi.com/products/fpga-soc/design-resources/design-software/libero-soc-polarfire#device-support

    Anyway, even for Windows only developers, the tools are years behind competitors just from ease of use and UI point-of-view. Microsemi should invest in more software engineers. Also in people to keep their documentation and website in sync.

    In terms of how well they’ve worked with Synopsys and internally on synthesis and PAR algorithms, who knows. In the end, Microsemi’s chips are slow compared to other vendors even with similar “up to” clock frequencies. Whether it’s due to hardware or software, I don’t know.

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