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An Actual Carbon Circuit

Go to any of the many semiconductor-related conferences, and you’ll see talk upon talk about 20- and 14-nm technologies. About planar transistors flipping up on their sides to create a sea of fins worse than your worst post-Jaws nightmare. About those fins subdividing into nanowires. And all of the permutations and combinations of every aspect of every step of every process involved in building usable beasts out of silicon.

But try to find some higher open ground so that you can get above all of this jostling. If you look hard way off in the distance, you can see a few people doggedly, hopelessly or hopefully, toiling away trying to turn pencils into circuits.

It’s the dream of the carbon nanotube (CNT). And it represents a huge shift away from what we’re used to. After all, the entire concept of the silicon wafer started as base material out of which transistors can be fashioned. With CNTs, foreign material is, for the first time, being put to use for the most intimate parts of the circuit. (OK, yes, epitaxy and sputtering and all the various kinds of deposition introduce new materials, but the heart of it is still silicon, even if you do grow more on top of the base wafer.)

That has forced researchers to rethink everything in the way we’re used to making chips, since the wafer now becomes merely mechanical and electrical support for the stuff going on in the CNT. And, over the last couple of years, lots of questions have been tentatively answered, at least for proof of principles. Can we grow or create CNTs? Yes. Can we get them onto the wafer? Yes. Can we manage the inherent chaos that comes with a semi-ordered bowl of spaghetti? Yes. Can we connect them up? Yes.

So if we can do all that, then we should be able to build stuff. Not just so that it looks proper (a challenge in its own right), but have it work electrically. And past efforts have yielded working transistors and ring oscillators and even basic logic elements like a D-type latch. All good; all useful.

The next obvious step is to build a “real” circuit – more than a simple element, but some kind of sub-system that demonstrably does something. This was undertaken by a team with contributors from Stanford and the University of Leuven in Belgium. They wanted to take on something non-trivial, but attainable – which suggests staying away from analog.

What they designed and presented at ISSCC was what they claim as the first full sub-system built entirely out of CNTs: a “fully-digital capacitive sensor interface.” Which turns out to be pretty convenient, since it’s built mostly out of ring oscillators and a D-type latch, blocks that have already been demonstrated. In high-level terms, the circuit involves a sensor-controlled oscillator (SCO) and a simple digital PLL, which itself consists of the latch (aka one-bit digitizer) and a digitally-controlled oscillator (DCO).

Terminology notwithstanding, it’s pretty straightforward. You’ve got two ring oscillators, one of which drives the D of the latch, the other driving the clock (or gate). Both of the oscillators have one stage with an extra capacitor loading the line. In the SCO, this is the capacitor you’re trying to sense. So the delay of this one stage of the SCO – and therefore its frequency – will depend directly and simply on that sensed capacitance.

The DCO, on the other hand, has a fixed capacitor loading one of the ring oscillator stages. That fixed capacitor can be switched in or out. So when it’s switched in, the DCO frequency drops; when it’s switched out, the frequency rises. The switch is controlled by the latch output: the extra cap is in when the output is 0 and out when the output is 1.

If you read the official description, it’s significantly more intimidating: it’s based on a “first-order Bang-Bang Phase-Locked Loop,” which apparently “resembles a first-order noise-shaped ??-modulator with single-bit quantization.”And here I thought it was a couple of ring oscillators and a D-latch…

Anyway… this was all implemented out of PMOS transistors (for convenience, not due to any inherent limitation); the ring oscillators involved nine stages of inverter, plus the extra cap and switch for the DCO; the D-latch involved another nine transistors. Easy, right?

Well, there are several steps to getting this right, many of which reflect work done before. So first they had to get a swatch of more-or-less aligned CNTs on their wafer. The gates for the transistors were under the CNTs, so those had to be put in place first. Then the CNTs were grown on a separate quartz wafer at around 800 °C and transferred onto the silicon wafer.

The transfer was done by first encasing the CNTs in gold and overlaying a tape; when this tape was pulled off, the gold and embedded CNTs came along with it. Once placed on the silicon wafer, the film was heated slightly such that, when pulled, the tape and softened gold came off, leaving the CNTs. This gave them a starting point of CNTs that were 99.5% aligned – not good enough – and that included metallic CNTs (mCNTs), which can cause shorts.

In our prior look at these particular CNT nemeses – misaligned CNTs and mCNTs, we saw that the Stanford team has devised a way of designing logic that ensures correct functioning even in the face of a few stray CNTs. They also have a way of, essentially, blowing up mCNTs so that they don’t end up shorting out transistors. Both of these techniques were used in the implementation of the circuit.

Note that the process of eliminating mCNTs relies on the fact that mCNTs break down at a voltage lower than their semiconducting brethren (sCNTs) do. It would be really nice if the breakdown distributions were separated far apart, allowing all mCNTs to be eliminated with zero damage to any sCNTs. Turns out that’s not the case; there’s a small range of overlap where, oh, how shall we say, there remain a few unpopped kernels of popcorn while the popped kernels are at increased risk of burning. They had to optimize their blow-out voltage, landing in the range of 9 V, where 99.99% of the mCNTs were destroyed and only 4% of the sCNTs were damaged.

As you might expect, our story has a happy ending: working circuits were achieved. In fact, they said that where they had circuit failures, there wasn’t an issue with the CNTs themselves, but rather some other more standard failure.

I’ll leave you to the proceedings (paper 6.8) to get the circuit and measurement details.

2 thoughts on “An Actual Carbon Circuit”

  1. CNTs have moved from tube to transistor to logic block to actual circuit. Is this technology on your radar yet, or does it still seem like science projects to you?

  2. Definitely, it’s been on my radar since the journal Science named Molecular Electronics as its “Breakthrough of the Year” for 2001. We gave a tutorial about it at ICCAD 2002. Back then it seemed litho would surely be finished by 20 nm and nano would save the day! Things change slower than we think sometimes. But the fundamentals remain.

    Since the nanotubes have to be handled en masse, there’s inherently a strong bias towards very regular structures. Hardwired logic is not very regular. So, the first commercially meaningful CNT logic devices are likely to be FPGAs.

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