Gardens are where your average Joe and Mother Nature can collaborate. (That is, “garden” in the American sense, not necessarily the British sense, which Americans would call a “yard.”) You decide where you want your plants – flowers, bushes, vegetables, whatever – and then you plant them. You might put down seeds or seedlings or plants that are already teenagers. They may or may not survive or thrive, but, at the very least (unlike human teenagers), you know where they will be.
My daughter got me a home mushroom kit a couple of weeks ago. It’s one of these things where you get a box that’s more or less a chunk of mycelium, and then you open it, and soak it and, lo, mushrooms appear at some point. Unlike the well-planned garden, however, you have no idea exactly where the mushrooms will sprout. They come up where they come up, and some may be bigger or smaller; it’s something you can’t really control.
Such a shift from planned to managed-random is occurring in the shift from standard silicon CMOS to carbon nanotubes (CNTs). Granted, CNTs are still very much in the research phase, but much of the work being done is targeted specifically at managing some of the unique random properties of CNTs.
A CNT is essentially a piece of graphene (which is a monolayer of carbon atoms in a honeycomb pattern) rolled up into a tube. Performance is anticipated to be many times that of silicon, at least in theory. Making that real is not quite so easy because we have less control – at least now – over CNTs as they’re born and bred.
With standard silicon, we create our devices much like we plan our gardens. We decide what goes where and then we build it there. Yeah, they don’t always work, but at least we know where they’ll be. By contrast, CNTs much more closely resemble the mushroom patch: they’re grown and, in the process, display the kinds of frustrating vagaries to which Mother Nature appears all too prone.
There are a number of different approaches to growing CNTs, many of which involve catalytic bits of other materials used to seed formation on some surface. The results can vary widely – different tube thickness or orientation – even tubes-within-tubes. Getting such a wild and wooly operation into shape for manufacturing would seem a challenge indeed.
One team that has been working on this extensively has been at Stanford, and you’ll see Prof. Subhasish Mitra presenting papers at numerous conferences discussing their approaches to these problems, and much of what follows comes from a distillation of those ideas. In particular, they’ve found that a quartz substrate forms a convenient surface for nucleating the formation of long tubes. Once grown, they can then be physically transferred onto a silicon wafer for further processing.
So ideally, then, you’d grow a uniform layer of closely-spaced parallel tubes as long as the substrate and then, once transferred to silicon, you would etch them to break them into the lengths needed for individual transistors – carbon nanotube FETs, or CNFETs – doping them and depositing metal for contacts over them. Sounds straightforward. Except that this is where nature makes things messy.
There are lots of variations that can affect these tubes, many of which have less impact in real circuits (more on that later). Two of them stand out in particular: the type of CNT (metallic or semiconducting) and, well, let’s call it “snaking” for now.
First, the type of tube. It turns out that, in this picture of rolling up graphene, it matters how you roll it. In particular, it matters how much you “twist” the tube. This is referred to as the “chirality,” and it results in some tubes acting like semiconductors – we want these – and some acting as simple wires. Wires aren’t bad if wires are what you want, but if you’re building a transistor, then a wire will simply short the source and drain together.
The problem is that, at present, you can’t control how the tubes will turn out. It’s a probability thing.
The second issue is what I’ve called “snaking.” I call it that because it’s essentially a failure of a CNT to follow the nice quartz crystal grain when growing. Instead it may be linear for a while, then wander off onto some other grain, and then continue growing linearly there. It’s like it jumped the tracks; physically, it can look like it’s snaking around rather than behaving like a nice straight line.
The problem here is that, if you’re planning on this tube going straight from the source to the drain of one transistor and instead, for example, it goes from the source of that transistor and suddenly jumps over to the drain of a different neighboring transistor, well, you’ve got yourself a problem. You’ve now changed the logic of your circuit.
What the Stanford team has been doing is going beyond just trying to improve the yield and behavior of the grown CNTs. It’s probabilistic, and even 99% semiconducting CNTs (sCNTs), for example, meaning 1% metallic CNTs (mCNTs), can still cause havoc. I’m assuming you wouldn’t tolerate 1% random wires showing up in your silicon circuit; yeah, it’s like that for CNTs. So the team has been focusing on mitigation strategies. How do you learn to live with this and manage it?
There are actually two priorities to the effects of this variation. The highest priority is ensuring that the circuit doesn’t outright fail. The second is ensuring that performance is relatively predictable.
In the first case, the team has identified some layout algorithms to eliminate the effects of snakes and mCNTs. The snakes can be eliminated by masking and etching them as they cross “tracks.” This typically happens in a kind of no-man’s land between a couple of transistors or gates, and the mask used to etch away unwanted metal to form the gates can also essentially be used to eliminate CNTs crossing over in that region. They claim that this layout algorithm can effectively cut the heads off of all these snakes.
Next is the issue of mCNTs, and the solution there is, once the transistors have been formed, to put a high voltage across the electrodes to blow out any metallic connections. The mCNTs are effectively treated like fuses and blown to remove them from the picture.
These techniques deal with the failure-inducing CNTs. What remains now is a question of performance. In fact, CNT variations can, according to Prof. Mitra’s team, rob a CNT circuit of 60% of the performance benefit over silicon at the 16-nm node. That’s a lot to give back after so much work.
Much of the issue comes from transistor correlation. In order to meet the drive current needs of most transistors, it will take several CNTs to make a transistor. In other words, there will be multiple CNTs going from the source to the drain, and the gate will cover all of them and treat them as one.
But the number of CNTs in a given transistor will vary. First of all, the density of CNTs isn’t consistent – some will be more closely spaced than others. This means that you may size your gate to cover, say, five CNTs, but in fact, sometimes it may end up covering four and sometimes six CNTs. That’s significant variation in the drive capability of the transistor.
Second, even if the density were uniform, some of the CNTs would be blown out because they were metallic. In fact, even in the snaking case, you may have a tube that starts on one track and ends up on another: along the left track, the higher transistors will use that CNT; lower transistors, below where it snakes off, won’t. And on the right, the reverse is true: higher transistors, above where the snaking CNT comes over, will have one less CNT than the transistors below it.
The Stanford team approaches this with layout rules and gate-sizing algorithms. For example, if two transistors need to correlate closely, you place them along the same CNTs so that they get the same density and mCNT effects (although presumably they can still be affected by snaking). The gate-sizing algorithm tries to find an optimal point where the delay penalty due to variation sensitivity is reduced for as little energy penalty (as you widen the gate) as possible.
There are other forms of variation besides these two: the Stanford team lists CNT diameter, alignment, and doping variations as other sources in their IEDM paper presented a few weeks ago. These would be very significant issues if each transistor relied on an individual CNT. However, because a transistor will use multiple CNTs, averaging makes these effects much less dramatic. Based on simulations they did, CNT count variations – due to mCNTs and density variation – accounted for a combined 37% of overall variation, while the other three components together amounted to 5%.
So the tidy gardening schemes we’re used to when building silicon FETs will need to give way to a more probabilistic approach, taking advantage of the shrooms where they happen to form. But, if the promise of CNTs is real and we learn to work with some of their untidy characteristics, we’ll hopefully get some magic from those mushrooms.