feature article
Subscribe Now

A Design Methodology for Building Process-Independent Hardmacro IP

Rapidly migrating intellectual property (IP) from one foundry to another and from one process node to the next can be a challenging, but necessary, part of the business, especially if the IP is generated and delivered as hardmacro IP.  That’s because hard IP or a GDSII netlist versus soft IP, RTL or gate-level netlist must be available for all major foundries and for a wide selection of process nodes at each foundry.

Designing new memory IP is largely a manual task that involves more analog circuits —charge pumps, voltage regulators and sense amplifiers, for example — than most logic designs.  At four megabytes (Mb), the design burden facing the layout manager and his implementation team is formidable. 

These issues are typical of memory design, and the Kilopass team ran into them when designing a recent 4-Mb memory IP block.  Its experience offers ways in which other teams can overcome these challenges.

To ease the burden, the team identified elements of the design that could be automated, freeing them to concentrate on critical analog elements that must be tailored for an individual foundry and process.  The result is an electronic design automation (EDA) tool flow developed for the latest anti-fuse non-volatile memory (NVM) product line. 

Exploiting the EDA Tool Flow

Using commercially available EDA solutions, the first task to be automated was rapid and accurate entry of design concepts, including managing design intent in a way that flowed naturally in the schematic.  This allowed designers to visualize and understand the many interdependencies of an analog or mixed-signal design and its effects on circuit performance.

In designing this 4-Mb memory, about 10 percent of the design required the layout team to import a GDSII netlist developed by another internal team.  The task of merging the existing layout with the rest of the memory design was a simple process requiring a day of manual place and route or connecting I/Os and routing power and ground. 

The team made use of the ability to embed design constraints in the netlist passed between the front-end design team and the implementation team.  Up until that point, those constraints were communicated by cryptic notes on the schematic.  For example:  Specify that two gates needed to be matched or a specific net is critical and its maximum length must not be exceeded in the layout.  Communicated the old way, when the schematic was given to the implementation engineer, the designer could only hope that the implementation team achieved the desired result. 

Managing Complexity

The implementation team built a new memory by creating a single memory cell then replicated it to build the more complex arrays — a bottom-up approach versus the conventional top-down approach that large digital SoC design teams employ.  The memory consisted of a bit cell comprising two transistors.  

Once the bit cell was created and optimized, the cell was replicated along a horizontal line of length n (32, for example), as specified in the schematic.  Once the line of memory cells was created, it was replicated vertically m number of rows (32, for example), as specified in the schematic.  In this manner, the implementation engineer created a 1-Mb memory array.  The process was repeated three more times to create the 4-Mb memory, a two-by-two matrix of 1-Mb arrays.

In developing the initial netlist, the front-end designer labeled each of the bit cells and its associated power, ground, bit line and word line.  He then specified the number of bit cells to be powered by a given power net to ensure that each cell received the same amount of current.

The ability to set constraints in the netlist passed to the implementation engineer ensured the design intent was captured in final layout. 

Automating Repetitive Manual Tasks

Automating repetitive tasks greatly reduced the time to complete the layout as well.  For example, labeling the bit line, word line, sense amplifier, and power and ground for a 4-Mb memory can take considerable time if done manually.  Surrendering the task to the EDA tool reduced the chore to a handful of keyboard operations.

In a pull-down menu, the implementation engineer completed a form that asked for the signal name, number of pins to be labeled, x and y coordinates of the first signal, spacing between pins, and the size of the text.  From this information, the design tool created each individual signal name.

Once the memory IP was implemented for the 40-nanometer (nm) process at foundry A, the layout team was confronted with converting the memory to 40 nm at another foundry.  With the automated EDA flow, this was reduced to a two-step process:  layer mapping followed by data manipulation.  In the first step, the mapping table for foundry A’s 40-nm library was replaced with the mapping table for foundry B’s 40-nm library.  The tool then automatically produced a layout for foundry B.  The process was not completely automated, as each foundry has its own unique rules; thus exceptions that do not map one-to-one are highlighted.

The implementation engineer examined all generated exceptions then made necessary adjustments.  For example, in foundry A, the bit cell may use layer C and D, whereas in foundry B, layer D and E are used.  Once the conversion was completed, a design rule check (DRC) was performed along with final verification. 

This automation took half the time compared with starting from scratch, enabling rapid migration of IP from one foundry to another.  While designing new memory IP, such as Kilopass’ Gusto anti-fuse NVM, continues to be mostly a manual effort, elements can be automated, enabling the layout and implementation team to concentrate on critical analog elements that must be tailored for an individual foundry and process.  

Author Bio:  Bernd Stamme is Director for Marketing and Applications at Kilopass Technology.  He has more than 15 years of experience in the IP and semiconductor industry. Prior to Kilopass, he was the Director of IP Technology at SiRF Technology managing the licensing and successful integration of third-party IP into SiRF’s GPS chip sets.  Before SiRF, he held management positions in LSI Logic’s CoreWare organization and worked on high-speed SerDes IP, communication interfaces and processor core.  Stamme holds a Dipl.-Ing. Degree in Electrical Engineering from FH Bielefeld in Germany.

One thought on “A Design Methodology for Building Process-Independent Hardmacro IP”

Leave a Reply

featured blogs
Jun 22, 2018
A myriad of mechanical and electrical specifications must be considered when selecting the best connector system for your design. An incomplete, first-pass list of considerations include the type of termination, available footprint space, processing and operating temperature...
Jun 22, 2018
You can't finish the board before the schematic, but you want it done pretty much right away, before marketing changes their minds again!...
Jun 22, 2018
Last time I worked for Cadence in the early 2000s, Adriaan Ligtenberg ran methodology services and, in particular, something we called Virtual CAD. The idea of Virtual CAD was to allow companies to outsource their CAD group to Cadence. In effect, we would be the CAD group for...
Jun 7, 2018
If integrating an embedded FPGA (eFPGA) into your ASIC or SoC design strikes you as odd, it shouldn'€™t. ICs have been absorbing almost every component on a circuit board for decades, starting with transistors, resistors, and capacitors '€” then progressing to gates, ALUs...
May 24, 2018
Amazon has apparently had an Echo hiccup of the sort that would give customers bad dreams. It sent a random conversation to a random contact. A couple had installed numerous Alexa-enabled devices in the home. At some point, they had a conversation '€“ as couples are wont to...