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Cell-Aware Fault Models for IC Production Test Outperform Gate-Exhaustive Fault Models

Physical defects within ICs, such as shorts and opens, can occur during manufacturing at any step along the fabrication process because of the complexity of modern CMOS technology nodes. The conventional approach to test for these physical defects includes structural tests using classical fault models such as stuck-at (SA), bridging [1,2], and transition faults [3]. This approach has efficiently addressed defects between standard cells and defects at input and output ports of library cells.

However, stuck-at fault models are insufficient for detecting faults and defects within cells [5,6]. Conventional stuck-at/transition test methods as well as the slow-speed or gross-delay cell-aware approaches cannot detect all cell-internal bridge defects. Thus, we had to move from using inter-cell fault models to intra-cell fault models. We found that the quality of test patterns improved significantly by explicitly targeting cell-internal bridge defects.

Stuck-at patterns also are insufficient to detect all detectable cell-internal bridge defects. Our previous experiments showed that only about 50% of today’s standard library cells are guaranteed to be tested sufficiently with stuck-at patterns.

A newly-developed cell-aware [4] automated test pattern generation (ATPG) methodology developed at Mentor Graphics addresses cell-internal defects and increases the defect coverage by about 1.2% compared to the defect coverage achieved with stuck-at patterns. This is equivalent to a reduction of 400 ppm in escape rate for a 50-mm2 design with an assumed yield of 90%; which is very essential in quality-driven markets where ppm targets are typically in the single digit range and below, traditionally requiring addition of application mode tests.

Recently, we conducted an analysis that compared the number of pattern sets needed for a gate-exhaustive pattern set in relation to a cell-aware pattern set. We evaluated the needed pattern sets to reach the maximum achievable coverage when applying the gate-exhaustive and cell-aware fault model on 1,500 library cells of a 65-nm CMOS technology and on 10 industrial designs.

Gate-Exhaustive and Cell-Aware View Generation

We started with generating gate-exhaustive and cell-aware library view files. In both cases, the pattern generation began with an ATPG model-generation step for all library cells used.

Cell-Aware Model Generation Flow

The flow for generating the cell-aware library view starts with the layout view of the library cell, for example, with the gds2 file of the cell. This is then followed by an analog fault simulation step to create library cell-internal defect-detection information. The defect-detection information (the defect matrix) is then input to the cell-aware synthesis step which calculates all optional test cubes for each defect inside the cell. Each optional test cube only contains the essential input assignments. Output of the cell-aware synthesis step is the cell-aware view of the cell, which is passed on to the cell-aware ATPG.

This library generation flow only has to be performed once for each technology node. The created cell-aware view can then be used for all designs. The generation flow is described in detail in [4] and is illustrated in Figure 1.

 

Hapke_Cell-Aware-Test_Figure-1.jpg

 

Figure 1: Cell-aware model generation flow.


Gate-Exhaustive Model Generation Flow

The flow for generating the gate-exhaustive library view starts with the netlist view of the library cell, i.e., the Verilog file of the cell. The generation of the gate-exhaustive library view is significantly simpler than the cell-aware view generation. The only information needed is the interface description of the cell, that is, the number of inputs and the port names. From this information, a simple tool can generate the needed exhaustive input cubes of the cell. The tool just has to write out a view file in a certain format which is equivalent to the one that is used for cell-aware models.

Results from CMOS 65-nm Library Cells

The following are details of our gate-exhaustive versus cell-aware evaluation. We evaluated the number of test patterns needed in the case of using the gate-exhaustive fault model and in the case of using the cell-aware fault model. We also evaluated the amount of defects for both fault models.

Gate-Exhaustive and Cell-Aware Pattern Sets

The graph in Figure 2 shows the number of test patterns needed for each library cell. For each cell, two values are shown in the graph:

  • the number of cell-aware patterns needed to detect all port stuck-at faults and all cell-internal bridges from 1 Ω up to 20 kΩ,
  • and the number of patterns for an exhaustive pattern set at the library cell inputs.

Hapke_Cell-Aware-Test_Figure-2.jpg

Figure 2: Number of gate-exhaustive patterns versus cell-aware per library cell.

 

This evaluation was performed on all 1,500 combinational cells of the CMOS 65-nm library.

The horizontal axis represents the individual library cells (from cell 1 to cell 1500). The vertical axis represents the number of test patterns required for each individual cell. The cells are sorted in descending order of their gate-exhaustive pattern count from left to right. The number of cell-aware patterns is shown as a reference.

Many cells require significantly more gate-exhaustive test patterns than cell-aware patterns. The cell with the largest number of gate-exhaustive test patterns is a multiplexer with 4 data inputs and 4 select inputs; that is, a cell with 8 inputs resulting into 256 gate-exhaustive patterns. In other technologies, cells with even many more inputs could be present, and, as such, the gate-exhaustive pattern count can easily be higher in other technologies or other library cells.

Gate-Exhaustive and Cell-Aware Defects

Looking at the number of defects considered for each library cell for the gate-exhaustive and the cell-aware fault models, we did not observe a big difference for the evaluated 65-nm library.

The cell with the largest number of gate-exhaustive defects is a multiplexer with 4 data inputs and 4 select inputs, that is, a cell with 8 inputs resulting into 256 gate-exhaustive defects. The same cell has 110 non-equivalent cell-aware defects for detecting 1-Ω to 20-kΩ bridges. For other technologies, or in case of cells with a larger number of inputs, the number of gate-exhaustive defects may increase significantly compared to the cell-aware case.

Results from Industrial Designs

We analyzed 10 different industrial designs to evaluate the pattern count and fault coverage figures for the gate-exhaustive and cell-aware fault model. The analyzed designs range from small designs (the smallest has 75,000 gates) up to large ones. The largest design named “I6649k” has 6.6 million gates, 457 thousand flip-flops, and 1,011 internal scan chains, resulting in 41.9 million cell-aware bridge defects and 21.6 million gate-exhaustive defects. The designs I1652k, I1676k, and I6649k use on-chip test compression; therefore, these designs have a high number of internal scan chains.

Pattern Count and Test Time

We performed two ATPG runs for each design (a gate-exhaustive and a cell-aware ATPG for each design), to investigate how many test patterns are required to test the designs with gate-exhaustive and cell-aware pattern sets. The ATPG results with respect to the number of patterns to test all testable faults are shown in Figure 3.

Hapke_Cell-Aware-Test_Figure-3.jpg

Figure 3: Number of gate-exhaustive patterns versus cell-aware per industrial design.

 

As can be seen in Figure 3, the number of gate-exhaustive patterns is significantly higher than the number of cell-aware patterns. The ratio for gate-exhaustive patterns compared to cell-aware patterns is on average 4 to 1. Note that the test time has a linear relation to the number of patterns as well as the test costs. Furthermore, a four-times larger ATE vector memory would increase the test costs even more as soon as the test patterns don’t fit into the vector memory; instead of using a low-cost test system, a high-cost test system may be needed on top of the four-times larger test-time.

Fault Coverage Figures

A well-used practice is to report the achieved fault coverage to judge the quality of test patterns. For established fault models like stuck-at, this is common use and very feasible. Targets around 98% or 99% are often reached. The same holds true for the recently introduced cell-aware fault model. The gate-exhaustive and cell-aware coverage results are shown in Figure 4.

 

Hapke_Cell-Aware-Test_Figure-4.jpg

Figure 4: Gate-exhaustive fault coverage versus cell-aware fault coverage.

 

The cell-aware fault coverage is on average about 98%. The gate-exhaustive fault coverage is on average only 66%. This means it is impossible to get a good correlation between the gate-exhaustive fault coverage and the quality of the patterns, which is in contradiction to the cell-aware fault coverage, where this correlation can be well-achieved.

Conclusion

We determined that the number of gate-exhaustive test patterns was about four-times larger than the amount of cell-aware test patterns. Test time and vector memory are affected by the larger pattern set. The resulting increase in test time is too costly for industrial production test.

In the case of the evaluated CMOS 65-nm cell library, the cell with the largest number of gate-exhaustive test patterns is a cell with just 8 inputs resulting into 256 gate-exhaustive patterns for the cell in isolation. In other technologies, or in case of other library cells with more inputs, the gate-exhaustive pattern count and test time increase can easily be significantly higher than four times, which would make the gate-exhaustive tests even more impractical. On the other hand, the cell-aware pattern set and test time is four-times smaller, but the quality of the cell-aware patterns is identical to the gate-exhaustive pattern set.

References

1. K.Y. Mei, “Bridging and Stuck-at Faults,” IEEE Transactions On Computers, vol. C-23(7), pp.720–727, 1974.

2. F.J. Ferguson and T. Larrabee, “Test Pattern Generation for Realistic Bridge Fault in CMOS ICs,” Proceedings of the IEEE International Test Conference, pp. 492–499, 1991.

3. J.A. Waicukauski, E. Lindbloom, B.K. Rosen, and V.S. Iyengar, “Transition Fault Simulation,” IEEE Design & Test of Computers, pp. 32–38, April 1987.

4. F. Hapke, R. Krenz-Baath, A. Glowatz, J. Schloeffel, H. Hashempour, S. Eichenberger, C. Hora, D. Adolfsson, “Defect-Oriented Cell-Aware ATPG and Fault Simulation for Industrial Cell Libraries and Designs,” Proceedings of the IEEE International Test Conference, paper 1.2, 2009.

5. I. Pomeranz and S.M. Reddy, “On N-detection Test Sets and Variable N-detection Test Sets for Transition Faults,” Proceedings of VTS, pp. 173–180, 1999.

6. F. Hapke, W. Redemund, J. Schloeffel, R. Krenz-Baath, A. Glowatz, H. Hashempour, S. Eichenberger, ”Defect-Oriented Cell-Internal Testing,” Proceedings of the IEEE International Test Conference, paper 10.1, 2010.

Author Bios

Friedrich Hapke is Director of Engineering Germany in Mentor Graphics Silicon-Test-Solution division. He mainly is involved in research and development of new methods and tools including defect-oriented testing, IEEE1687, ATPG, logic BIST, boundary scan, and failure diagnosis. His interests also include electronic design automation in general for deep-submicron technologies. Friedrich holds a diploma in Electrical Engineering from the University of Applied Science Hamburg, Germany. Before joining Mentor Graphics, he had various R&D management positions at NXP and Philips Semiconductors. Friedrich is the author and co-author of many publications and holds over 20 patents in the area of design for test.

Stefan Eichenberger received a PhD in Science (Physics) from the University of Zurich, Switzerland. He joined NXP (then Philips) in 1993. He is a senior principal engineer at NXP Semiconductors, Nijmegen, The Netherlands. His research interests include defect-based testing, diagnosis, and yield learning.

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