In space, no one can hear you reconfigure.
Space has always had a love/hate relationship with FPGAs. On the one hand, FPGAs are the best technology ever for space use. They eliminate the huge NRE cost associated with extremely low-volume ASIC design, they provide the possibility of in-flight reconfiguration in a location where service calls would be… expensive, to say the least, and they help get that expensive bird in the air faster with their short, low-risk design cycles.
On the other hand, SRAM FPGA technology has always been extremely uncomfortable with radiation, which, in space, is plentiful. Since the configuration logic and all of the sequential and memory elements rely on SRAM-like structures, a single wayward neutron can ruin your whole day – flipping a bit where you least expected it and causing strange things to happen very quickly.
There have been, to date, three sub-optimal solutions to this problem. Actel has long marketed rad-hard anti-fuse FPGAs that could stand up to the rigors of space deployment. The downside of these devices is lower-than-SRAM density combined with a lack of in-flight reconfigurability. A couple years ago, Actel partially addressed the reconfigurability issue by rolling out their line of flash-based FPGAs for space use. While these devices allowed reconfigurability, they still didn’t have the speed or density of SRAM FPGAs, and they didn’t have the radiation resistance to sustain higher orbits – as is required for geosynchronous satellites.
The third option we’ve had (until now) for space-bound FPGAs was effective but very ugly. Basically, Xilinx took a regular commercial FPGA die, hacked it up with bailing wire, duct tape, and WD-40 (not literally, of course), and made it where it would kinda’ sorta’ work in space. The radiation mitigation techniques applied to these devices included regular scrubbing of the configuration data, triple-module redundancy on most of the storage elements, a bunch more redundancy on critical parts of the design, and a huge corresponding loss of density, performance, and power efficiency. In short, making an SRAM FPGA radiation-tolerant gave back a lot of the benefits that led one to choose an SRAM FPGA in the first place.
Last week, we talked about Mentor’s new Precision Rad-Tolerant synthesis tool, which takes a lot of the work out of making a design space-worthy with current-generation FPGA technology (click here). For people using the duct-tape and bailing-wire method, Mentor can now automatically apply the duct tape for you.
Now, Xilinx is launching a brand-new rad-hard FPGA family that could be a game changer. Instead of continuing their studies in the Rube Goldberg School of FPGA Radiation-Mitigation (as with previous generations), they’ve designed a new chip specifically for the rad-hard market. The new device comes with storage elements that, as far as we can divine, don’t have the usual single point of failure. The company isn’t saying exactly how they hardened these elements, but we surmise that there must be more than one place the state is held. Xilinx says that this new design eliminates the requirement for triple-module redundancy (TMR) in your design and configuration scrubbing – the combination of which took a huge toll on previous-generation rad-tolerant FPGAs.
Radiation mitigation built into the architecture includes rad-hard, dual-node configuration latches, configuration and JTAG control logic hardened with built-in TMR, dual-node latches and SET filters on user registers and IO block registers, and DCI logic controllers hardened with embedded TMR with independent and redundant error detection and correction. Block RAM has built-in error detection and correction as well.
The result is a completely new kind of rad-hard FPGA family. This family should have the full performance, density, reprogrammability, and functionality of conventional, commercial-grade SRAM FPGAs, while attaining a level of radiation immunity previously seen only with one-time-programmable anti-fuse devices. This means that, for the first time, an FPGA with state-of-the-art capability can be used in high-radiation environments such as geosynchronous orbit – without extensive compromise in the design for radiation mitigation.
This also marks the first time that FPGA-based SerDes has been available for rad-hard design. SerDes is a fantastic match for space-based systems because wide parallel busses can be replaced by differential pairs, operating at a much higher data rate and with much better error detection and correction. All those pins and traces saved reduce size and weight – which are at a premium in spacecraft, as well as increasing the overall reliability of the system by minimizing connectors, and reducing the power-per-bandwidth requirement for moving data around your satellite.
In space, power is weight and weight is money. It has been estimated that the cost to put one pound into orbit is as high as $10,000. On the ground, when we need to dissipate more heat, we add things like fans to move air… oh, that doesn’t work. Neither do conventional heat sinks. In fact, most of the excess thermal energy has to be carried by conduction through the circuit board to the outside and radiated into space. All that conducting and radiating capacity adds weight. Larger solar panels and power supplies also dramatically increase weight and system complexity. The elimination of many of the extensive mitigation techniques and the reduction of redundancy also improve power consumption. Less power dissipated in the FPGA means smaller power supplies and reduced heat dissipation requirements in the system. The result – much more capability can be packed into the same or smaller size and weight profile.
The new Xilinx space family (well, device, actually) dubbed Virtex-5QV is based on the Virtex-5 (65nm) family, but, unlike previous space families, this one is a different die from the commercial counterpart. The XQR5VFX130 (That’s a nerd part number for sure!) launches with an SEU latchup immunity of <100 Mev-cm2/mg, a configuration cell upset rate of <10-10 Upsets/Bit-Day, a functional interrupt rate of <10-10 Upsets/Bit-Day, and a total ionizing dose of >700 kRad(Si). Ready to blast off with one now? Wait, there’s more. With the reduced need for mitigation techniques, the device makes 130K logic cell equivalents available (we’ve discussed this many times before, but that means that Xilinx thinks the number of 6-input logic cells is about the same as 130K 4-input LUTs.) It has about 10Mb of integrated block memory, and 320 DSP48E slices that can run up to 360 MHz. Combined with 450MHz “system performance,” these features should make the device ideal for high-performance DSP and computing applications. Getting this data onto and off of the device are the usual complement of IOs along with 18 multi-gigabit serial transceivers. These applications may now be done in orbit with the results sent down to earth instead of doing the computation on the ground with the raw data packages being transmitted back.
Xilinx thinks the devices will be useful for applications like SDR modems (raising the specter of partial reconfiguration of FPGAs being done in space – which may be a little mind boggling for some old-school LUT-heads), sensor/radar processing, and reconfigurable fault-tolerant computing. For those of you who noticed the “FX” in the part number and thus suspected that this device might also include an embedded PowerPC or two – it doesn’t, but nice try.
Since Xilinx has built the radiation mitigation into the architecture, we surmise that the same techniques will scale relatively easily to subsequent Xilinx product generations (such as their 40nm and 28nm families). The company points out that it uses no process-related mitigation techniques, so the rad-hard devices are made with the same process as the commercial ones.
If all blasts off as planned, this Xilinx family is poised to dominate the high end of the space market. It will likely seek out new applications and explore new worlds of performance in space-bound electronics as well as in a few radiation-susceptible earth-bound ones.
