feature article
Subscribe Now

The End of Silicon Valley

A moment of silence, please, for Silicon Valley. Intel announced last week it would close its chip-manufacturing plant located near the company’s headquarters in Santa Clara – and with it, the very last chip fab anywhere in Silicon Valley.

The technology that gave its name to the Santa Clara valley, once called “the valley of heart’s delight” for no immediately obvious reason, has left for greener pastures. When I started working in electronics, Santa Clara still had fruit orchards in it. Chip plants alternated with cherry trees. Now there’s no silicon in Silicon Valley. (There’s still plenty of silicone jiggling around the valley, but that’s a different story entirely.)

The rise of Silicon Valley has been chronicled elsewhere, but the short version involves the happy confluence of universities, talent, and cheap land. Two of those three still exist in abundance in Santa Clara county (you guess which ones). A quick perusal of online real estate listings shows that modest houses anywhere near Intel Galactic Headquarters start at about $1 million for an aging fixer-upper.

But it’s not housing costs that drove the fabs away. It’s what’s under the soil, as in tectonic plates. As semiconductor technology became more advanced the fabs and foundries became exquisitely sensitive to dust, contamination, and vibration. The merest disruption could ruin a week’s worth of chip production, consigning several millions of dollars of silicon to the dumpster. That’s exactly the kind of plant you don’t want to build over an earthquake fault.

The awesome cost of a fab – and their occasionally awesome profitability – also meant chipmakers like Intel went looking for more favorable tax environments. Oregon, Arizona, New Mexico and states or even countries further afield offered lucrative incentives for locating fabs within their borders. Anywhere that land was cheap, flat, and geologically stable the local government could provide the rest: roads, clean water, an educated workforce, and deferred taxes. Silicon Valley was where chips were designed; Singapore, Ireland, and Idaho were where they were fabricated.

Perhaps coincidentally, Intel’s chairman of the board, Craig Barrett, announced his retirement the same week as the plant closing. The man who, along with Andy Grove and Gordon Moore, helped define Intel and drove its success may have felt the passing of this milestone more keenly than most. Throughout his tenure, Intel had always manufactured chips within sight of his corner office. If the fab goes, I go, he may have thought. It’s getting too late in the day for both of us.

And so this week we mark the retirement of two Silicon Valley landmarks that gave the area its flavor and its very name. Let’s all remember to explain to future generations how that name came about.

Leave a Reply

featured blogs
Apr 25, 2024
Structures in Allegro X layout editors let you create reusable building blocks for your PCBs, saving you time and ensuring consistency. What are Structures? Structures are pre-defined groups of design objects, such as vias, connecting lines (clines), and shapes. You can combi...
Apr 25, 2024
See how the UCIe protocol creates multi-die chips by connecting chiplets from different vendors and nodes, and learn about the role of IP and specifications.The post Want to Mix and Match Dies in a Single Package? UCIe Can Get You There appeared first on Chip Design....
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...

featured video

How MediaTek Optimizes SI Design with Cadence Optimality Explorer and Clarity 3D Solver

Sponsored by Cadence Design Systems

In the era of 5G/6G communication, signal integrity (SI) design considerations are important in high-speed interface design. MediaTek’s design process usually relies on human intuition, but with Cadence’s Optimality Intelligent System Explorer and Clarity 3D Solver, they’ve increased design productivity by 75X. The Optimality Explorer’s AI technology not only improves productivity, but also provides helpful insights and answers.

Learn how MediaTek uses Cadence tools in SI design

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

Autonomous Mobile Robots
Sponsored by Mouser Electronics and onsemi
Robotic applications are now commonplace in a variety of segments in society and are growing in number each day. In this episode of Chalk Talk, Amelia Dalton and Alessandro Maggioni from onsemi discuss the details, functions, and benefits of autonomous mobile robots. They also examine the performance parameters of these kinds of robotic designs, the five main subsystems included in autonomous mobile robots, and how onsemi is furthering innovation in this arena.
Jan 24, 2024
13,494 views