feature article
Subscribe Now

Sun Shines on Xilinx

64-bit OpenSPARC for Multi-Core Research

Today’s high-performance, multi-core processing systems are complicated beasts – from both a hardware and a software perspective.  Developing the architectures, protocols, interconnects, and software development tools and methodologies that can take advantage of multiple 64-bit processors working in collaboration can’t be done on a chalkboard.  It’s an exercise that requires extensive prototyping, trial-and-error, and experimentation. 

Unfortunately, “experimenting” with implementations in monolithic silicon is impractical for any of us that don’t moonlight managing hedge funds.  When there is a seven-figure price tag and a few months of turnaround time for each “test,” that adventurous spirit that leads us to “just give it a try” quickly goes out the window.  This is complicated by the fact that state-of-the art architectures are mostly proprietary and those pesky lawyers don’t appreciate us mucking about in patented and trademarked waters. 

What we need is a vehicle that allows researchers to experiment with reasonable cost and turnaround time, and with a design that allows us access to the architecture without access to a legal defense fund.  Luckily, Sun and Xilinx have teamed up to put together a solution that addresses this problem.  This week, the two companies jointly announced a new development kit, distributed through Digilent, that will allow researchers to create applications targeting Chip Multi-Threading architectures (CMT). The platform uses Xilinx FPGAs to implement soft-core versions of the OpenSPARC T1 64-bit CMT architecture design. 

For those that have been under a virtual rock in the processor world for the last couple of decades, SPARC (Scalable Processor ARChitecture) is the reduced instruction set (RISC) processor architecture that has powered Sun servers and workstations since the late 1980s.  In about 2006, Sun was cleaning out their basement (as we all do from time to time) and came across this perfectly good proprietary processor architecture that had a lot of good use left on it.  They did the socially-responsible thing and threw it in the Gnudwill pile.  OK, maybe that’s not quite fair.  Sun has a long history of open-sourcing high-value IP.  In this case, they took the Verilog source code for a competitive commercial processor architecture and made it open-source, allowing researchers and commercial entities alike to use, re-use, and enhance it (almost) at will. 

Open-sourcing a high-performance, well-proven, 64-bit processor was a bold and basically unprecedented step.  It gave developers and researchers a fantastic starting point for CMT work, lowering the barriers to research and development significantly.  One barrier it didn’t lower, however, was what to do with all that Verilog source code.  You could load it up on a simulator and trudge along at glacial speeds, not really doing much learning, or you could spring for an ASIC project for each attempt, investing something like the debt of many small countries in the process. 

This is where the Xilinx connection comes in.  The 32-thread OpenSPARC T1 core takes up something like 40,000 LUTs on a Xilinx device, so a Virtex-5 LX110T (a Virtex-5 device with 110K LUT equivalents and multi-gigabit serial transceivers) will have about 70K LUTs left over for user experimentation.  Xilinx mounted one of these on an ML505 development board (which usually comes equipped with a 50K LUT device), and by stitching several of these boards together using the SerDes interconnect (Aurora over Serial ATA), one can create a multi-core system with an arbitrary number of processor cores – all in programmable logic. 

Xilinx and Sun are partnering to deliver the new boards along with open source RTL, documentation, and tools.  Projects like RAMP (Research Accelerator for Multiple Processors) are expected to take advantage of the platform to do research on everything from the multi-core architecture itself to the challenge of creating software optimized for processing environments with an arbitrary number of processor cores.   In the move from ever-faster monolithic processors to many-core environments, our traditional assumptions about everything from programming languages and styles to compilers to operating systems shift dramatically.  By using FPGA-based prototyping platforms, systems can be run at reasonable speeds so that complex operating systems and applications can reasonably be tested.

In order to get the party started faster, Sun and Xilinx have created a joint University donation program that allows academic professors to apply for grants (that’s secret code for free development boards, we think) for qualified research and teaching projects.  If you want one for commercial use, you’re free to order it immediately from Digilent at the regular price.  The companies say it is available now.

Sun claims that over 9,000 OpenSPARC T1 and OpenSPARC T2 RTL files have been downloaded since the OpenSPARC program was initiated in 2006.  Besides being a boon to CMT research, it will be interesting to watch the effect and efficacy of further development of a complex processor architecture by an open source community.

Leave a Reply

featured blogs
Aug 16, 2018
Learn about the challenges and solutions for integrating and verification PCIe(r) Gen4 into an Arm-Based Server SoC. Listen to this relatively short webinar by Arm and Cadence, as they describe the collaboration and results, including methodology and technology for speeding i...
Aug 16, 2018
All of the little details were squared up when the check-plots came out for "final" review. Those same preliminary files were shared with the fab and assembly units and, of course, the vendors have c...
Aug 15, 2018
VITA 57.4 FMC+ Standard As an ANSI/VITA member, Samtec supports the release of the new ANSI/VITA 57.4-2018 FPGA Mezzanine Card Plus Standard. VITA 57.4, also referred to as FMC+, expands upon the I/O capabilities defined in ANSI/VITA 57.1 FMC by adding two new connectors that...
Aug 14, 2018
I worked at HP in Ft. Collins, Colorado back in the 1970s. It was a heady experience. We were designing and building early, pre-PC desktop computers and we owned the market back then. The division I worked for eventually migrated to 32-bit workstations, chased from the deskto...
Jul 30, 2018
As discussed in part 1 of this blog post, each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store its configuration bits. The time required to pr...