ChipX has long spanned the gap between FPGA and ASIC. Their range of products includes everything from structured ASIC through standard cell, and they’re often called into service when FPGAs can’t cut the mustard because of cost, power, or performance, but a full-blown minimum-geometry ASIC project is beyond the means of the project.
Now, they’re rolling out something they call “Hybrid ASICs” to make their span even more continuous. Before we get into specifics, let’s have a brief review of terminology. FPGAs are standard semiconductor products. FPGA companies build and inventory devices, and all of your customization is done after the device is completed. One step up the custom ladder from there are the (almost) defunct gate arrays. These devices are pre-built with a sea of unconnected gates, and they are customized by adding only the last few layers of metal that define the interconnect between the gates.
One notch more advanced than gate arrays (we’d still call ‘em gate arrays if we could get away with it) are gate arrays with more complex hard-wired IP blocks also built into the fabric. These devices are known as “structured ASICs” (although vendors are now steering away from that label because the title has earned somewhat of a black eye in the market.) Now, instead of having to build those multipliers out of discrete gates, you can just hook up to an already-optimized one lying there in wait. These devices are also customized by adding just the last few layers of metal.
There’s still quite a gap between structured ASIC and Standard Cell, however, and ChipX has now bridged that gap with two distinct technologies. The first of these, which we wrote about almost a year ago, were their “Embedded Arrays” – devices with a mixture of standard cells for performance and structured ASIC fabric for customizability. Now, the new hybrid ASIC slides in between embedded arrays and full-blown standard cell designs.
Think of hybrid ASIC as a roll-your-own platform chip. You build most of your design (the part that won’t be changing often) using standard cell technologies. This part of your design might contain things like processor cores, memory, peripherals, and some I/O. Yes, it can even include analog (calm down, we won’t mention it again). Most companies designing products with a number of variants have a basic platform that acts as the starting point, and the goodies that distinguish one variant from another represent a very small percentage of the whole design. For this small percentage, ChipX drops in a block of structured ASIC fabric. You can use this to quickly spin product variants without re-designing (and without paying the extra NRE for) the basic platform.
With the hybrid ASIC approach, you can have a lot of the best of both worlds. ChipX claims that derivative devices based on a previously designed platform can shave off $300K-$400K per design on NRE. More importantly, derivative development effort decreases by 2-3 months. Given the value of time-to-market today, those months could eclipse the NRE savings in value.
ChipX doesn’t make a big deal of it, but overall risk is also drastically reduced with this approach. Once a platform has been proven, your main vulnerability is in the much smaller (and usually simpler) application-specific structured ASIC section. This means more time for you to do actual design work, and less time spent polishing your resume “just in case” an extra re-spin points the bottle at you.
This hybrid ASIC approach also lets you divide your team into efficient groups. One group can be responsible for the design, verification, and evolution of the basic platform. They can catch the latest processor cores, keep up with the proven I/O standards, and make sure that the teams working on value-added variants can focus on bringing home the bacon.
The new ChipX Hybrid ASIC family is dubbed CX6800, and it’s based on the company’s 130nm process. The custom platform is designed just like the company’s standard cell offering, with the structured ASIC core dropped in just like any other hard-macro IP. ChipX can customize the structured ASIC fabric to be any size, so you’ll want to plan your platform with just enough room for future expansion (and then double that, if our experience counts for anything.)
ChipX gives two application examples for the new platform. The first hypothesizes a base design with CPU, peripherals, memory and flash controllers, and all the interstices required to build a basic embedded computing platform on a chip. Then, a 400K SA section is dropped in for the “application specific” hardware. In total, the device would consume a total of 1M usable gates, provide 1.2 Mb usable memory, and fit in a 456PBGA package. Each derivative product would then be built faster and cheaper and with less risk than with a conventional standard cell approach.
The second example rolls the complete application into the platform area – exactly as one would with a standard cell. This time, however, 200K gates of structured ASIC fabric are included for future use. In most projects, this would be used for future enhancements, standards changes, and rapid tracking of marketing’s unpredictable whim. Again, NRE and development times for future variants would be drastically reduced.
ChipX is focusing the new platform on applications like Video CODECs (where each variant on the platform could support one or more specific standards), Media Access Controllers launched pre-standard for quick time-to-market with the ability to re-spin when the standard stabilizes or to easily provide variants for multiple standards, encryption engines where the product line could be rapidly updated if the protocol was compromised, and protocol encoding where a number of protocols could share the same basic platform design – using the SA section for protocol-specific hardware.
For companies in businesses with narrow market windows and highly-specialized product variants, the Hybrid ASIC could be a major enabler, getting products to market fast while saving significantly on NRE investment and financial risk. It fills an important gap in the continuum between programmable logic devices like FPGAs and high-risk, long lead-time custom silicon like standard cells. It also gives companies a chance to gain competitive advantage by developing highly relevant structured-ASIC-like platforms optimized for their particular product lines.