They say that history repeats itself. Unfortunately, however, we find that this is often not true in debug mode. That elusive set of conditions that precipitated the problem we’re pursuing often fades into obscurity when we try to capture, observe and analyze them. Take, for example, the problem of debugging system-on-chip ASIC designs or any complex hardware system where massive quantities and varieties of real-world stimuli are required to give your design the thorough shaking-out it needs to capture that once-in-a-blue moon bug in the act. In that case, there’s a constant battle between performance and visibility. You need your system operating at real-world speeds with real-world stimuli to create the conditions for many bugs to occur, but gaining enough visibility under those conditions to establish cause and effect is often difficult.
Synplicity is tackling this problem head on with an innovative new technology they call “TotalRecall.” TotalRecall is a technology (no product has yet been announced) that is designed to beef up FPGA-based verification by adding a new level of visibility to real-time debugging and verification. Normally, instrumenting an FPGA-based prototype introduces additional resource requirements and overhead that preclude at-speed operation, and visibility is still limited. In addition, connection back to the HDL-level design is usually tenuous or difficult because the tools that understand HDL are not typically available in the FPGA-based prototyping environment.
TotalRecall addresses both of these problem areas. The approach is clever, elegant, and deceptively simple in concept. Basically, there are two copies of your design running in two identical FPGAs. The first copy contains your crash-test dummy. That’s the one that will probably veer off course and hit the wall. The second copy is your secret debug weapon. It follows along behind, mimicking the exact behavior of the first copy, using the exact same stimuli. When the first copy hits the bug, the system pauses and saves the complete state of the second copy (the one that hasn’t hit the bug yet). You’re starting to get the picture now, aren’t you? With full knowledge that the bug is about to occur, and the complete pre-error design state saved, the events leading up to the crash of the second copy of the design can be closely scrutinized. In fact, they can be exported to an HDL simulator where the full visibility and control of software simulation can be applied to locate the cause of the problem.
Rather than thinking of TotalRecall as a visibility extension to our FPGA-based prototyping environment, it might be helpful to think of it as a hardware acceleration extension to our HDL-based simulation environment. This is because the process actually begins when we are developing our HDL code. We can set up HDL-based assertions to trigger the breakpoints we want to examine. In simulation, these assertions can apply only to our simulation-based stimulus – our HDL testbench. However, when we move execution of our design into an FPGA-based implementation, we can stimulate it with real-world inputs. TotalRecall will trigger our HDL-based assertions when the hardware implementation of our design hits a bug and will gather the essential state information from the shadow copy, preparing us to debug and analyze back in our RTL/HDL-based simulator debug environment.
Synplicity has patented this technique, which promised to give us the best of both running tests at full hardware speed and chasing down bugs with software/HDL debugger control and visibility. At this time, they are making a “technology only” announcement. While they say that customers are currently testing the technology, the company is not yet announcing a specific product or projecting availability.
One interesting aspect of this announcement is the collaborative nature of the complete solution. To work properly, this technique obviously requires an HDL simulator and debug environment (products not currently offered by Synplicity) and a specially modified FPGA development board (a hardware product most likely to come from a third-party vendor already in that business). This means that, at a minimum, Synplicity will probably be partnering with at least one EDA company that is normally a competitor and at least one hardware company producing prototyping boards or systems. The parts of the equation that sit squarely in Synplicity’s home turf are the synthesis of the assertion-trapping into the FPGA hardware and the mapping of the data from the post-synthesis hardware implementation back to the pre-synthesis RTL/HDL domain for debugging in the simulator.
In order to cover the breadth of the market, of course, Synplicity will have to cover more than one hardware platform and at least the most used simulation environments. Toward this end, the company says they will be working with partners from their “Partners in Prototyping” (PIP) program – an alliance of companies including Altera, AMO GmbH, ARM, The Dini Group, EVE, Flexody, GiDEL, HARDI Electronics, Nallatech, ProDesign and SK-Electronics Co. that have agreed to work with Synplicity to develop prototyping flows using Synplicity tools.
TotalRecall should be an exciting addition to the debug arsenal for design teams trying to locate and eliminate the elusive problems that occur only occasionally, problems that depend on particular sequences of stimuli amidst a sea of possibilities, or problems that exist in the interstices between hardware and software. For many designers, the capability will finally put teeth into the use of HDL assertions and may influence more teams to create their HDL designs and IP with assertions built in.
Synplicity says that more information on products containing the new technology will be available in 2007. Until then, we’ll have to be content with finding our bugs the old-fashioned way.