If the value of structured ASIC as a gap-filler between programmable logic and cell-based ASIC is still in question, there are at least two companies on opposite sides of that gap where a decision has clearly been made. Both LSI Logic and Altera unveiled new families this week aimed at attacking this new and potentially lucrative segment of the silicon landscape. Interestingly, both companies’ involvement in structured ASIC can be viewed as a defensive move. As a leading supplier of cell-based ASICs, LSI shored up its defenses against attack from the other side of the FPGA/ASIC border a couple of years ago by creating its RapidChip structured ASIC family. The low-risk, low-NRE, high-performance solution provided a welcome alternative for design teams that were possibly about to fall off of LSI’s radar due to skyrocketing NREs for cell-based ASICs.
On the Altera side, structured ASIC poses a threat to the high end of the FPGA price/performance curve with a more potent product that mitigates the ASIC NRE penalty. With their introduction of HardCopy structured ASICs, they employed the “join them” strategy by offering up their own structured ASIC solution, with the kicker of a smooth migration from FPGA-based prototyping and early production, straight into structured ASIC cost-reduction.
LSI Logic’s Integrator2 is a significant step-up from their previous RapidChip structured ASIC families, or “platform ASIC”. LSI has been in the structured ASIC game about as long as anyone now, and they’re taking advantage of what they learned in their first-generation families. Integrator2 is based on the 110nm technology of their recent Integrator series, but it adds heaping helpings of additional memory as well as compatibility with now-mainstream DDR memories. Companies in communications, storage, computing, and networking will find Integrator2 a much more satisfying meal for their voracious memory appetites.
Starting with the I/O ring, Integrator2 is designed to be compatible with DDR2, QDR2, RLDRAM2, FCRAM2 and other emerging high-performance memory standards. Along with an available Denali DDR controller, this gives Integrator2 head-of-the class external memory interface capabilities. For system applications that demand large amounts of off-board RAM, Integrator2 is a considerable step-up from RapidChip’s first generation.
With many customers wanting to integrate applications that previously required several large FPGAs, it was critical that the new RapidChip have a large and flexible internal memory offering as well. Integrator2 has a configurable finer-grain Matrix-RAM architecture that LSI claims will allow easier mapping from other memory architectures (such as the FPGAs in your prototype) with improved memory utilization in real designs. The Matrix-RAM consists of a configurable block made up of many identical RAM tiles. Low routing overhead for the tiles offers less waste, whether creating shallow/wide or narrow/deep configurations, and allows 300MHz performance across the entire Matrix.
The Integrator2 family consists of 8 slices, ranging from about 1.3M to 5.6M usable ASIC gates, 359 to 1024 user I/Os, and 1.1 to 7.9 Mbits of embedded RAM. The five largest members of the family also have a “landing zone” that can accommodate an ARM966 processor as well as other specialized hard IP. All of the memory is true dual-port with both read and write on both ports.
LSI says that the Integrator2 makes the RapidChip family an attractive option, both for traditional ASIC customers looking for a lower NRE, faster time-to-market solution that can meet their design specifications, and for FPGA consolidators looking to integrate and cost-and-power-reduce a multi-FPGA solution into a single mask-programmed device. Given the density range of the Integrator2 family, it seems to be correctly placed to accomplish both tasks.
A hidden advantage of the structured ASIC approach for teams accustomed to cell-based ASIC solutions is the cost and simplicity of the development environment. With a single seat of cell-based ASIC tools running well into the realm of six-figure price tags, LSI placed a premium on providing a smooth tool solution with a price tag that wouldn’t defeat their low-NRE value proposition. Their RapidWorx solution is licensed on a time-based model that should allow teams plenty of access to complete their project without consuming much design tool budget. The tools were also developed by companies such as Synplicity with an eye to FPGA-like ease of use and approachability. The result is an affordable, accessible tool suite that should get you up and designing very quickly.
When it comes time to migrate to an even lower unit cost platform, LSI offers a smooth migration path to their cell-based families. Interestingly, this is comparable to the migration path touted by FPGA vendors like Xilinx and Altera, from their FPGA solutions to their higher-volume cost-reduced offerings. If you want to go from FPGAs all the way to a cell-based ASIC, however, you’ll have to get off and change technologies at the structured ASIC level. Like most commercial airline trips, non-stop service is not available.
Meanwhile, over on the FPGA side of the silicon gap, Altera is rolling out the latest version of its HardCopy structured ASIC line, known as HardCopy II. For those already familiar with Altera’s HardCopy strategy, this is hardly a surprise. HardCopy is a mask-programmed structured ASIC device with a one-to-one mapping to a corresponding Altera FPGA. Altera’s first HardCopy was based on its Apex family, and it followed with another version based on its popular Stratix FPGAs. Since Stratix II, (the new 90nm version of Stratix) was announced last year, it logically followed that Altera would announce a HardCopy version of those devices as well. A few months and a few million mask-dollars later, HardCopy II has hit the wire, and it should be a successful sequel to the HardCopy story.
As FPGA vendors have eyed the gap between FPGA and ASIC, and watched with wary eyes the emergence of structured ASIC technology, the two FPGA-industry leaders, Xilinx and Altera, have chosen differing strategies for fending off the structured ASIC foe. While Altera has taken the HardCopy path, creating true structured ASIC families based on their programmable products, Xilinx has answered with EasyPath, a lower-priced version of the original FPGA.
Contrasting Altera’s and Xilinx’s approach, Xilinx will always have an advantage getting their cost-reduced family quickly into production following the corresponding FPGA family because there’s no re-engineering to do. Altera, on the other hand, will probably take longer to get their structured ASIC into production, but will reap benefits such as higher performance, lower power, and broader applicability. As a result, Xilinx customers can use EasyPath to get cost-reduced FPGAs into production very quickly, even on the latest FPGA families. Altera customers may have to wait longer, but can even design up-front with the intention of targeting HardCopy II for production, taking advantage of its higher performance and other ASIC-like characteristics.
Since both FPGA vendors’ solutions are based on a one-to-one replacement for their high-end FPGA devices, they will not necessarily compete directly with structured ASIC offerings like LSI Logic’s RapidChip. While there is some overlap in density between Altera’s largest device in their new HardCopy II line and LSI Logic’s new Integrator2 family (1M to 2.2M ASIC gates for HardCopy II vs. 1.3 to 5.6M gates for RapidChip Integrator2), LSI claims that most of their “FPGA Integration” business is from integrating multi-FPGA designs into a single RapidChip device.
In comparison with the LSI line, Altera’s new family will facilitate very smooth transition from an FPGA-based prototype or early production system because of the exact one-to-one mapping between Stratix II devices and HardCopy II devices. Like its Stratix II twin, HardCopy II is based on a 90nm process, giving it a nice performance boost, and the largest device weighs in with 8.8Mbits of internal RAM, giving it an even higher RAM-to-logic ratio than the LSI devices. HardCopy II also includes embedded high-performance DSP hardware on the high-end models, just like the corresponding Stratix II devices.
Looking more closely at the architecture of HardCopy II, Altera has added another trick to its repertoire in scaling from FPGAs to HardCopy structured ASIC. In their first-generation HardCopy Apex line, they simply replaced the configuration circuitry with mask-programmed metal to convert the FPGA into an ASIC. With the second-generation HardCopy Stratix, they also optimized the hard-IP blocks for the structured ASIC version. With HardCopy II, they have attacked the ALM module itself (Altera’s variable-input look up table) by creating hard modules that are one-to-one replacements for various ALM configurations. This gives an additional area reduction and a corresponding boost in performance with improved power efficiency. Altogether, Altera claims HardCopy II delivers a 50-70% core power reduction versus the corresponding Stratix II device.
Another benefit of the HardCopy II solution is the design tool flow, which is essentially the same as for Stratix II. Combined with the small NRE and attractive unit price structure ($15 for 1 million ASIC gates), HardCopy II provides a compelling solution, both for FPGA users seeking to cost reduce and for projects that are thinking structured ASIC from the beginning. HardCopy II will be squarely in competition for even relatively high-volume, high-performance consumer applications, where Altera’s products would not have previously been in contention.
What do these announcements tell us? Their message is two-fold: first, that structured ASIC still has all the appearances of a technology/methodology that will earn a long-term spot in the custom IC palette between FPGA and standard cell ASIC; second, that vendors from both sides of the gap view structured ASIC as a high-stakes emerging market and are willing to invest substantial resources to both protect their existing businesses and to gain control of a chunk of this emerging technology space.