As programmable systems become increasingly complex, a rich ecosystem of technology is growing up to support the diversity of new designs that take advantage of the flexibility and time-to-market advantages afforded by today’s FPGA platforms. Every time the market presents a new opportunity, another startup or established player steps forward with a solution that advances the state of the art. Let’s examine a few of the more recent ones in detail, starting from the beginning of the design process and walking through to the working hardware.
Design Melée Management
Before you can push your design down to a development board, you need to have your initial implementation and architecture in place. Whether you’re assembling IP from a variety of sources, cranking out VHDL or Verilog code, or moving from Matlab or another high-level language down to hardware, you’ll need to capture and verify the functional behavior of the major components of your design. As the back-end of FPGA design (logic- and physical-synthesis, place-and-route, timing closure) becomes more automated and trouble-free, the design schedule bottleneck is squeezed forward to the beginning of the process.
Portland, Oregon-based Stelar tools recently announced their solution for design teams developing and integrating HDL modules into a coherent design. Their HDL Explorer is designed to help design teams with what Stelar calls RTL closure. “RTL closure is the process of getting your design clean before synthesis,” says Steve Sapiro, Vice President of Marketing at Stelar. “By analyzing and cleaning your design, you shorten your development time and reduce both functional errors and costs.”
Stelar contends that over 80% of designs are re-works of previous projects. With a typical large design containing thousands of modules and teams often geographically scattered and experiencing turnover, the task of understanding and checking the validity of legacy and external IP is huge. Stelar’s HDL Explorer is an intelligent graphical tool for visualizing, navigating, checking, and integrating all those modules in a way that significantly simplifies the job of understanding and unraveling the chaos.
Particularly powerful in the Stelar solution is the use of the concept of “best known methods” (BKMs). Stelar’s tool allows design teams to capture otherwise elusive organizational expertise in an organized and useful fashion. BKMs can be used for purposes such as checking for known recurring errors, implementing HDL coding styles, or suggesting efficient implementation methods based on rules captured and created by internal experts. This facilitates a kind of institutional learning process that is otherwise difficult to stimulate in today’s typical dynamic engineering environment.
HDL Explorer takes just minutes to pick up and provides an extremely easy-to-navigate graphical tree view of the design that shows the organization and status of your design at a glance. Unlike many graphical design viewers, this one seems to understand that most real designs are bigger than your thesis project, and that you don’t always want to wait until you have the complete design assembled and organized before you can use any tools to help you manage it.
You’ll also have some new sources for all that IP that’s going into your next design. One of them might be OmniWerks who is debuting their new “IP Done Right” model of licensing which cuts through the traditional red tape of IP acquisition and integration. They designed their IP use model with FPGA designers in mind. For a fixed fee, you get a one-year, one-developer, one-company license with perpetual maintenance rights. Their delivery is based on Altera’s SOC Builder framework, and their first commercial product is a high-quality PCI core. OmniWerks cores can be purchased and downloaded online with a credit card, so you probably won’t have to take the dreaded walk down to the purchasing department to get the cores you need to keep your design on schedule.
In addition to integrating IP, many application areas can benefit from the use of higher levels of design abstraction. Poseidon Systems’ new Triton Tuner and Triton Builder tools aim to help you raise your level of abstraction. You can simulate your design with transaction-level modeling technology, and then use Poseidon’s tools to partition and evaluate the hardware and software partitioning of your SoC design at the architectural level.
Triton Builder is essentially a high-level synthesis tool, but unlike most companies fielding high-level synthesis technologies, Poseidon has chosen not to focus specifically on digital signal processing. Instead, they are applying their technology to the problem of partitioning complex hardware-software systems into embedded software combined with synthesized hardware accelerators for compute-intensive tasks.
Triton Tuner is a transaction-level simulator loaded with features for analyzing and optimizing hardware/software systems. It offers features for analyzing and optimizing memory hierarchy. It also allows software to be tuned for better performance by profiling and identifying hot-spots that could be improved or moved into custom hardware.
Already well established in the C-based algorithm-to-architecture space, Celoxica has released a new version of their popular DK design suite. In addition to general feature and performance upgrades, Celoxica’s DK Design suite version 3.1 adds support for Xilinx’s new Virtex 4 and Altera’s new Stratix II and Cyclone II platforms. Celoxica combines C synthesis technology with a suite of verification capabilities, including their own custom boards, to facilitate hardware-in-the-loop design and debug. As the veteran in C-based design for FPGAs and ASIC prototypes, Celoxica’s success is a bellwether for the adoption of higher-level alternatives to RTL design.
The critics of programmable logic have historically relied on a three-pronged mantra as the basis of their arguments: density is too low, performance is too slow, and power consumption is too high. With recent generations, the density and performance barriers have been broken for a wide variety of applications. Power now remains the Achilles’ Heel of FPGA adoption. While the dynamic power consumption of programmable devices has steadily dropped from generation to generation (on a per-gate, per-frequency basis) the rhetoric has steadily heated up. Now, the largest suppliers are taking the power perception seriously and launching a plethora of power-reducing solutions to help cool the controversy.
Xilinx recently announced Spartan 3L, a low-power version of their popular Spartan-3 series. While 90nm has gotten a bad rap for power consumption, the real issue is quiescent or static power caused by leakage current. Dynamic power is actually better than previous process nodes. Spartan 3L attacks the static power problem by providing a “hibernate” mode that puts the device in a low-power offline state when it’s not being actively used. Upon return to active duty, the device is reconfigured and ready to run again. Hibernate mode provides up to a 98% reduction in quiescent power. For shorter cycles, a “standby” mode offers up to 68% less power drain. Think of the new modes the way “standby” and “hibernate” work on your laptop (although hopefully much faster).
Across town, rival Altera is also looking at the power problem with the latest release of their Quartus II design tool suite. Version 4.2 of Quartus II includes what Altera calls its PowerPlay technology, which is a set of capabilities for analyzing and optimizing power consumption in your FPGA design. PowerPlay begins with a set of early analysis spreadsheets that can be used at the beginning of the design cycle to estimate power. As the design progresses, more detailed information and models, including functional and timing vectors and actual device resources used, are taken into account, providing increasingly accurate power estimates.
Of course, all the estimates in the world won’t help if you can’t do anything about them, so Altera is also planning push-button power optimization capabilities in place-and-route that leverage the estimation engine to bring down overall power consumption. The potential of power optimization tools has thus far barely been tapped in the FPGA market. FPGA companies have historically sold primarily to customers who don’t place a priority on power, but with the new wave of applications arriving at their door, vendors are pulling their collective heads out of the sand and investing heavily in development of power-reducing technology.
Whether you’re struggling with a mass of mysterious VHDL or Verilog, coping with C-based design, or perplexed by power problems, these new solutions are just a taste of what’s on the roadmap for the next 12 months. Based on our early editorial contacts, 2005 promises to bring an unprecedented number of new product announcements in the world surrounding programmable logic. From innovative new design tools to new implementation technologies to new ready-made modules with FPGAs already on them, the industry will announce a variety of interesting offerings to help your ideas make their way into working hardware and onto the market faster, more reliably, and with less effort than ever before.