Introduction
The risks associated with ASIC solutions increase in magnitude with the move to smaller process geometries. This coupled with the increase in design complexity is compelling companies to look for viable technology options that offer low unit and total costs, high-level of system integration, wide selection of IP, design flexibility with faster time to market, and no/minimal incremental design or design tool investment. Such alternatives must also avoid the pitfalls of ASICs that include high NRE and re-spin expenses, slow turn around times, and complexity of the design environment and ecosystem, and hidden costs of conversion, verification and development.
This article will compare two such alternatives — (customer-specific) FPGAs and Structured ASICs. Structured ASIC product offerings tend to be similar to FPGAs in that they have pre-defined combinations of gates, memory and I/Os. However, their architectures tend to trade off flexibility in favor of reduced area in order to achieve their cost targets. Yet, in reality the vast majority of designs that are expected to go into volume production are initially prototyped in an FPGA. Ultimately, the decision becomes a risk-reward evaluation of the migration path from an FPGA to Structured ASIC conversion or to the new class of customer-specific FPGAs that offer a conversion-free path to high volume production devices priced below Structured ASICs.
Design Conversions
On the surface, it seems economical to migrate to an ASIC once a design is finalized. However, conversions are not as seamless as promised by Structured ASIC vendors. In fact, it is fraught with risks and hidden costs of conversion.
The first consideration faced by designers is mapping the final design to the target architecture,. This revolves around the mapping of the logic, I/O and memory resources from an FPGA to a Structured ASIC. FPGAs generally tend to have columnar memory architectures and offer an efficient means to form larger memory structures when required. On the other hand, the use of distributed memory blocks in some Structured ASIC architectures can pose problems when large contiguous blocks are required by design. The need to join together blocks that are physically separated to form a larger block that is logically monolithic can increase congestion in routing. This not only can adversely impact the access times of those memory structures, it may also leave fewer routing resources available for logic thus impacting design performance.
Another challenge inherent with Structured ASIC conversions has to do with pad limitations, especially as process nodes shrink. To get an adequate number of pads, Structured ASIC vendors sometimes have to grow their die size and increase the effective cost to end customers. This problem is compounded by the fact that Structured ASIC I/Os tend not to be as flexible as FPGA I/Os. To keep I/O structures small and less area intensive, Structured ASIC vendors have to make some difficult choices about what standards they want to address and how. For designs requiring large buses of input and output I/Os (e.g., SSTL2 buses for SDRAM or HSTL buses for certain telecom protocols), the limitations in I/O designs can make it difficult to achieve pin compatibility in the FPGA to ASIC conversion. This scenario often results in either a board re-spin or a migration to a larger device – both unpalatable options. Apart from memory and I/Os, there are a whole host of issues such as difficulties with mapping other clocking and I/O structures such as PLLs and high-speed transceivers that designers should consider while re-targeting their FPGA designs to Structured ASICs.
High-end FPGA families provide fully featured platforms of embedded hard IP such as MGTs (Multi-Giga Bit Transceivers) and Ethernet MAC Cores. FPGA vendors offer a rich portfolio of soft IP that are qualified for their FPGA architectures and need to be qualified for the target ASIC. With Structured ASIC conversions, designers must consider IP availability, design conversion and the royalty associated with the use of the IP in the targeted Structured ASIC devices. Even when suitable IP is available, it may not be silicon-proven in a particular Structured ASIC vendor’s proprietary architecture, thus exposing companies to unnecessary risks.
Apart from the actual design conversion, consider the daunting task of design verification and qualification. Once the design has been remapped to a Structured ASIC, it must be verified and debugged to ensure that it complies with the original specification. This involves significant amounts of time and valuable resources developing test benches or test vectors and working with Structured ASIC vendors’ engineering teams to ensure functional verification. In addition, once prototypes are delivered, the customer has to redesign and qualify the system with the prototypes delivered by the Structured ASIC vendor before fully qualifying the design for production. Structured ASIC customers must also maintain a suite of expensive EDA tools to ensure compliance with their vendor’s handoff format requirements, often complicated by mismatch of tool versions between the end customer and Structured ASIC vendor. These issues significantly increase the costs in terms of cycle time, design tools and manpower that are better utilized on more value-added tasks.
Customer-specific FPGAs offer a viable alternative to Structured ASIC conversions. They are identical in functionality and timing to the standard FPGAs on which a design is prototyped – the only difference being that the latter are completely programmable while the former are not. As a result, memory mapping and performance achieved is identical to that achieved in a standard FPGA. The one-to-one mapping between such customer-specific FPGAs and standard FPGAs extends over Look-Up-Tables, Memory, I/Os, IP and all features in the Standard FPGA to overcome the problems associated with design conversions from FPGAs to Structured ASICs. Also, there is no additional IP royalty, design tools or engineering costs associated with the move to volume production.
Time to Market
Time to market is even more important in the age of shrinking geometries and shorter product life cycles. Since Structured ASIC vendors only customize the top few mask layers in the fabrication phase, they are able to offer compressed lead times when compared to Standard Cell ASICs. With customer-specific FPGAs, the prototype fabrication/evaluation phase of a Structured ASIC is completely eliminated and companies can go directly to production.
Once a design has been frozen, the cycle time required to bring the design to market with a Structured ASIC has three phases. The first is the elapsed time from RTL (or design handoff) to prototype sample delivery. Typically, this takes from four to eight weeks depending on the design complexity, vendor lead times, etc. This is followed by the prototype qualification phase, a very important and often overlooked part of the time-to-market claim.
Once a Structured ASIC vendor delivers prototype samples, the end customer has to perform detailed verification/qualification of the prototypes to ensure that the silicon meets the original design specifications prior to volume production. This can vary from one to three months accounting for time to discover and fix any problems and also qualify the end system with the prototypes. Occasionally, re-spins may be required adding to cost and time to market.
Once the design is qualified and prototypes approved, the vendor may take an additional 12 to 14 weeks for delivering production parts. Overall, the time to volume production can take anywhere in excess of 20 weeks not accounting for any major bug fixes or re-spins. Since it is a custom solution, even a minor re-spin or a bug can set back schedules by an equal amount which can prove very costly in the long run. Studies show that a four-week delay in product rollout results in a 14 percent loss of market share for customers.1 See Figure 1.
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Figure 1.
SOURCE: CURRENT AND EMERGING EMBEDDED MARKETS AND OPPORTUNITIES – ELECTRONICMARKET FORECASTERS † SOURCE: MCKINSEY & CO. , #SOURCE: JOHN CHAMBERS WINDRIVER SYSTEMS, INC.t |
One solution to mitigate this problem is to use standard FPGAs for prototyping and seamlessly move to customer-specific FPGAs in production without any additional steps in between. With standard FPGAs, time to market is almost instantaneous. The advantage of customer-specific FPGAs, such as EasyPath™ FPGAs from Xilinx, is that companies can go directly from design freeze to volume production in eight weeks. Since such FPGAs are identical to the corresponding FPGA prototypes, the entire prototype evaluation cycle is eliminated. Companies can get production parts in significantly less time than it takes Structured ASIC vendors to provide prototype silicon. Shorter lead times not only mean faster time to market, they also allow design teams to adjust the design freeze milestone as needed to accommodate the demands of a fast-changing marketplace.
The Lowest Total Cost Solution
The path to lower cost for Structured ASICs comes about primarily as a result of customizing fewer mask layers per design. For example, a typical 0.18-micron Standard Cell design uses six customized metal layers (and the vias in between) and a 0.13-micron design uses eight metal layers (and the vias in between). Structured ASIC vendors use the top few (typically two to four) metal layers only. The base modules are all buried in the lower layers with their ports coming up to the programmable layers. During the fabrication phase, the connections between various ports are made to realize the requisite logic. This approach has both cost and architectural implications.
Structured ASICs have fewer customized top layers which imply that companies only pay for what they use and get NREs that are lower than corresponding Standard Cell ASICs. On the other hand, Structured ASIC architectures tend to have a fair amount of overhead burden that reduces the amount of routing resources available for a particular design. As a result, the final routed densities, measured in KGates/mm2 (that directly determines the silicon real estate customers pay for), tend to be significantly lower than Standard Cell architectures. The number of customizable mask layers (metal and vias included) a vendor uses, to a large extent, is proportional to the magnitude of routed gate densities that are achievable. However, a higher density implies a higher NRE and vice versa.
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Figure 2.
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Figure 2 shows the comparative economics of standard cell ASICs, structured ASICs, standard FPGAs, and customer-specific FPGAs. FPGAs have traditionally offered a zero-NRE, low-upfront cost solution. Standard cell ASICs have a high NRE and a relatively low unit cost, but with the overhead discussed earlier. Structured ASICs promise to lower the NRE at a unit cost that is higher than that of standard cell ASICs, but lower than that of standard FPGAs. With the new class of customer-specific EasyPath FPGAs from Xilinx, companies now enjoy unit prices as well as NREs that are lower than Structured ASICs. Customer-specific FPGAs provide the lowest total cost solution for volume production through a combination of factors — industry’s lowest NRE charges (starting at $75K), low-cost design tools and IP, prices below structured ASICs, fastest times to production and a conversion-free path to implementation.
Flexibility to Make Design Changes
One of the major advantages of FPGAs over ASICs is the flexibility to make design changes in case of a specification change or design error. Traditionally, designers have had to forgo this advantage as they move from FPGAs to an inflexible custom solution like standard cell or structured ASICs.
However, recent developments by Xilinx in customer-specific FPGAs now preserve some of the flexibility of the FPGA while also maintaining a low cost approach.
Xilinx Spartan-3™and Virtex-4™ EasyPath FPGAs enable companies to buy a custom device that supports two applications or two variations of the same design. For example, companies can use one bit-stream to perform system diagnostics on the entire system and the other to load the second application-specific bit-stream. In addition, designers can change LUTs and I/Os even after these devices have been deployed in the field. For instance, a line card in a router might need to have the drive strength (and slew rate) adjusted a notch or two depending on what load it encounters. Companies can implement a range of drive strengths that are available for certain I/Os. This new level of customer-specific flexibility offers a unique blend of FPGA-like features at (or below) ASIC-like prices.
Selection of Platforms
Structured ASIC vendors can roughly be grouped into two camps based on their ability to address IP-centric designs. Some vendors have a wide portfolio of embedded IP, while other companies can only address generic designs. Most vendors typically offer a choice of 8 to 15 devices across a couple of product families. Generic designs are those that require nothing more than gates, memory and I/Os. While some Structured ASIC vendors focus exclusively on this segment, almost all vendors have product families at 0.18-micron and 0.13-micron that can address these needs. This class of designs tends to be very price driven due to increased competition. For designs that require a lot of IP such as PowerPC processors, DSP or Ethernet MACs, the translation to a Structured ASIC vendor often requires a revalidation of the IP on the vendor’s silicon platform.
With customer-specific FPGA solutions, designers have to access the same wide range of validated IP as with the standard FPGAs. The bottom line is that whether it is a generic design or an IP-centric design, customer-specific FPGAs offer very competitive and cost-effective solutions for high volume migration as compared to Structured ASICs.
Conclusion
The path to volume production need not be hard for companies looking for the right combination of feature-sets at the lowest cost and fastest turn around times. Table 1 highlights the most notable differences between Structured ASICs and customer-specific FPGAs.
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Table 1: Structured ASICs vs. Xilinx EasyPath customer-specific FPGAs
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Structured ASICs attempt to fill the niche between FPGAs and Standard Cells. However, they fall short on the promise due to the high hidden costs of conversions, longer lead times and lack of flexibility — all of which are easily addressed by FPGAs, be it standard FPGAs or the new class of customer-specific FPGAs. With a seamless one-for-one conversion-free path for customers across a wide portfolio of product families and FPGAs, customer-specific FPGAs allow companies to get to production volumes much faster and at lower prices than with Structured ASICS.
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About the Authors Gokul Krishnan is a Sr. Marketing Manager with the Market Specific Products Division at Xilinx, where he is responsible for new product directions and market opportunities for the EasyPath FPGAs. Gokul has 10+ years of experience in technical and marketing roles in FPGAs, Structured ASICs and Optical Networking. He holds a B.S. from Indian Institute of Technology in Madras, a Ph.D from the University of Notre Dame, and an MBA from the Wharton School of Business. Balaji Thirumalai is a Senior Marketing Manager with Xilinx, where he is responsible for the worldwide marketing of EasyPath FPGAs . Balaji has 10+ years of industry experience in FPGAs, EDA and semiconductor technologies in various engineering and marketing roles. He holds a B.E. in EE from the University Of Madras, India, an M.S in EE from the State University of New York at StonyBrook, and an MBA from the Haas School of Business at U.C. Berkeley. |
1 John Chambers, CEO Cisco Systems Inc.
