editor's blog
Subscribe Now

Simpler CDC Exception Handling

For static timing analysis, it’s a concept that goes back years. You get a bunch of violations, and then you have to decide which ones represent false paths or multi-cycle paths and create “exceptions” for them. Tedious.

Well, apparently formal analysis can have the same issue. Only here they’re referred to as “waivers,” according to Real Intent. If you run analysis and get a long list of potential violations, you have to go through the list and, one by one, check them for “false positives” and mark them as such. Time-consuming and error-prone. And tedious. Especially when working on large-scale SoCs (so-called “giga-scale”).

In their latest release of Meridian CDC, which does clock-domain crossing verification, Real Intent has provided a different way of handling this: provide more granular control over the run parameters in the form of rules or constraints that can be successively refined.

Using the old method, if a particular over-reaching aspect of analysis caused 100 false positives, you’d have to find all 100 and “waive” them. With the new approach, when you find the first one, you make the refinement, and then, with a rerun of the analysis, the one you found and the other 99 all disappear. OK, not disappear per se, but they’re grouped together as not being an unexpected finding. You can also review that list to make sure nothing snuck through. (This is a simplification of a more sophisticated overall process, but it captures the essence.)

This may take some iterations, but in the end, you can have a clean run with no exceptions, and the way you got there is less likely to have involved a mistake here or there.

You can find out more about Real Intent’s latest Meridian CDC release in their announcement.

Leave a Reply

featured blogs
Jul 20, 2018
https://youtu.be/KwrfcMtbMDM Coming from CDNLive Japan (camera Asushi Tanaka) Monday: Nicolas's Recipe for Digital Marketing in EDA Tuesday: Embargoed announcement Wednesday: Trends, Technologies, and Regulation in China's Auto Market Thursday: Breakfast Bytes Guide...
Jul 19, 2018
In the footer of Samtec.com, we'€™ve always made it easy to contact us by phone, email, or live chat (even fax back in the day!). To continue to progress this theme, you'€™ll now find a new helpful tool in the footer area of Samtec.com. This tool will match you up with yo...
Jul 16, 2018
Each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store the eFPGA'€™s configuration bits. Each Speedcore instance contains its own FPGA configu...
Jul 12, 2018
A single failure of a machine due to heat can bring down an entire assembly line to halt. At the printed circuit board level, we designers need to provide the most robust solutions to keep the wheels...