editor's blog
Subscribe Now

Keeping DDR Performance Fresh

DDR memory timing is tricky business. Especially with later versions of the standard, the timing for each memory on a module has to be carefully determined; there’s no such thing as just issuing a read or write to all the chips together. A further problem, however, is that the timing is subject to change based on a number of factors, including environmental conditions and wear-out.

Some companies address this by doing a power-up calibration that involves reading and writing to figure out the optimal timing. But things can still drift as the system warms up or the box gets moved into the sun or the environment changes for any of a number of other reasons.

Uniquify, a company whose business has morphed from ASIC design services into an IP company (with further evolution underway) has earned a patent on dynamic recalibration – the ability to keep tuning the timing during use. The prior barrier had been the fact that writing to the memory for calibration purposes is destructive. That’s not a problem at startup, before anyone has started using memory, but while the system is running, the application has control of the memory, and there is little appetite for setting a bit of it aside for use only by calibration.

Uniquify’s approach was to use application memory, but copy and store the current contents of the calibration location, do the calibration, and then replace the contents so that the application never notices it missing. The timing of this recalibration can be set to coincide with refresh or at some other designer-defined interval.

The calibration looks both for drift in the timing window as well as changes to the width of that window. Each recalibration finds the edges of the window and recenters the strobe. But if the window closes, then a specific error is flagged.

You can find out more in their latest release.

Leave a Reply

featured blogs
Apr 25, 2024
Structures in Allegro X layout editors let you create reusable building blocks for your PCBs, saving you time and ensuring consistency. What are Structures? Structures are pre-defined groups of design objects, such as vias, connecting lines (clines), and shapes. You can combi...
Apr 25, 2024
See how the UCIe protocol creates multi-die chips by connecting chiplets from different vendors and nodes, and learn about the role of IP and specifications.The post Want to Mix and Match Dies in a Single Package? UCIe Can Get You There appeared first on Chip Design....
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured paper

Designing Robust 5G Power Amplifiers for the Real World

Sponsored by Keysight

Simulating 5G power amplifier (PA) designs at the component and system levels with authentic modulation and high-fidelity behavioral models increases predictability, lowers risk, and shrinks schedules. Simulation software enables multi-technology layout and multi-domain analysis, evaluating the impacts of 5G PA design choices while delivering accurate results in a single virtual workspace. This application note delves into how authentic modulation enhances predictability and performance in 5G millimeter-wave systems.

Download now to revolutionize your design process.

featured chalk talk

Achieving Reliable Wireless IoT
Wireless connectivity is one of the most important aspects of any IoT design. In this episode of Chalk Talk, Amelia Dalton and Brandon Oakes from CEL discuss the best practices for achieving reliable wireless connectivity for IoT. They examine the challenges of IoT wireless connectivity, the factors engineers should keep in mind when choosing a wireless solution, and how you can utilize CEL wireless connectivity technologies in your next design.
Nov 28, 2023
20,138 views