editor's blog
Subscribe Now

Xilinx’s Crossover

Xilinx announced their new Zynq family a while back, and now they’re working the positioning to further clarify why it’s different from past processor+FPGA combo chips. At Mentor’s U2U, Xilinx CTO Ivo Bolsens described Zynq as a “crossover” chip, sharing the characteristics of an FPGA, ASSP, and ASIC.

And here’s what he said makes the critical difference: coherency. An FPGA typically resides outside the processor’s known realm, and is responsible for managing its own memory – and for keeping the contents consistent with the main CPU memory if necessary.

In Zynq, by contrast, the FPGA gets access to the main memory. That means less data copying, since the processor can simply send a pointer to the FPGA for some accelerated function. The FPGA and the CPU are, more or less, peers – it’s multicore with shared memory, only with one of the cores being an FPGA. And the FPGA doesn’t need its own memory manager.

As subtle as that seems, it can make a big difference in how you conceptualize the interplay between CPU and FPGA. And, presumably, removes some glue logic and speeds performance.

Leave a Reply

featured blogs
Jul 18, 2018
I recently talked with Mr Takizawa of TDSC about their use of Cadence's Interconnect Workbench (IWB). You may not recognize those initials. Toshiba split itself into three companies last year and one of them is TDSC, or Toshiba Electronic Devices & Storage Corporatio...
Jul 16, 2018
Each instance of an Achronix Speedcore eFPGA in your ASIC or SoC design must be configured after the system powers up because Speedcore eFPGAs employ nonvolatile SRAM technology to store the eFPGA'€™s configuration bits. Each Speedcore instance contains its own FPGA configu...
Jul 12, 2018
A single failure of a machine due to heat can bring down an entire assembly line to halt. At the printed circuit board level, we designers need to provide the most robust solutions to keep the wheels...